JTAG Logic Analyzer

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Hello everyone,,

Ok, I went down the rabbit hole and am just now coming up for breath!


After an epic week long battle that found me obsessed with this one task I have something pretty cool working on the Papilio.


Let me start from the beginning, at the end of last week when I was working on the new board design I realized that there might be a huge problem with trying to connect the channel A UART pins from the FT2232 to FPGA I/O pins. I pulled out the trusty Papilio One and tested it out, sure enough, when the Papilio is being programmed all of the I/O pins go to 3.3V which will interfere with the TCK and TDO pins during jtag programming. So the way I had things wired up was not going to work. I started thinking about solutions, adding an IO switch would solve the problem but I'm not super thrilled about doing so. So I started thinking about why we need it connected and it really comes down to being able to use channel A for communications after the FPGA is programmed. Well, we already have an example of doing that, we use the bscan primitive to program SPI Flash...

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So I thought, well before I commit to adding an IO switch to the board I should spend a couple days connecting the Sump Logic Analyzer to the bscan primitive so we can use the FT2232 channel A or logic analyzer debugging and use channel B for normal uart communications to our Soft Processor. It's going to be hard to do but I should be able to bang it out in a couple days... Famous last thoughts...


Every day I made just enough progress to keep me completely obsessed for the next day, just a little bit more and it will be working... Well it dragged on way longer then I expected but I have a first working prototype! There are still some bugs to squash but it is working well enough to prove that we can use channel A for debugging and there is no need to add an IO switch to the new board

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