Chris Wilcox Posted June 22, 2018 Report Share Posted June 22, 2018 I'm working through Mike's excellent book and am on the 1 bit (Delta Sigma) DAC chapter 16. I've also taken some time to peruse the Xilinx App Note 154 that is referenced in the chapter. In para 16.4 of the book, the VHDL 'code' in para 16.4 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dac8 is Port ( Clk : in STD_LOGIC; Data : in STD_LOGIC_VECTOR (7 downto 0); PulseStream : out STD_LOGIC); end dac8; architecture Behavioral of dac8 is signal sum : STD_LOGIC_VECTOR (8 downto 0); begin PulseStream <= sum(8); process (clk, sum) begin if rising_edge(Clk) then sum <= ("0" & sum(7 downto 0)) + ("0" &data); end if; end process; end Behavioral; The meat of the work is done here: sum <= ("0" & sum(7 downto 0)) + ("0" &data); This makes sense and works quite nicely on my DUO/Logicstart. I tested this using switches for the Data input and output the Pulsestream to an LED. My confusion concerns how this is implementing the Delta Adder in the App Note (which is actually a merge as explained in the App Note). I've managed to pretty much wrap my head around the App Note theory, but cannot understand why the copies of the MSB are not prepended to the sum(7 downto 0) element. Thanks, -Chris Quote Link to comment Share on other sites More sharing options...
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