dindea Posted June 19, 2018 Report Share Posted June 19, 2018 Programming the flash of Papilio PRO with a new FPGA application will require erasing the flash or a part of it. My question is: How much will be erased? The entire flash or only so many blocks that the application will occupy? Or "something in between", e.g. "always 2 MBits"? Or the number of blocks occupied ny the greatest possible application for SPARTAN6, by assumption different for ...LX4 and ...LX9? Quote Link to comment Share on other sites More sharing options...
Thomas Hornschuh Posted June 19, 2018 Report Share Posted June 19, 2018 Normally it just erases the number of blocks the new bitstream occupies. Quote Link to comment Share on other sites More sharing options...
dindea Posted June 20, 2018 Author Report Share Posted June 20, 2018 Thank you for the info, Thomas Hornschuh. It was as I hoped. But what do you mean by "Normally"? Are there cases when the entire flash is erased? Anybody who knows or has an idea about the "worst-case" size of a SPARTAN6-LX9 bitstream? I.e. the size of the bitstream for the largest possible SPARTAN6-LX9 application. Quote Link to comment Share on other sites More sharing options...
mkarlsson Posted June 20, 2018 Report Share Posted June 20, 2018 See page 77 in this document: https://www.xilinx.com/support/documentation/user_guides/ug380.pdf The flash chip is erased in units (aka sectors) of 64kB so programming a 65kB bitfile will erase a 128kB area. Magnus Quote Link to comment Share on other sites More sharing options...
Thomas Hornschuh Posted June 20, 2018 Report Share Posted June 20, 2018 11 hours ago, dindea said: Thank you for the info, Thomas Hornschuh. It was as I hoped. But what do you mean by "Normally"? Are there cases when the entire flash is erased? A non compressed bitstream has always the same size which directly relates to the type of fpga. For a spartan-6 lx9 it is around 330KByte (when I remember it right, I‘m currently traveling so I cannot check). But it is possible to attach additional data to the bitstream e.g. with a program like bitmerge http://hamsterworks.co.nz/mediawiki/index.php/Config_flash or the -a option of papilio-prog This additional data can than be read with a spi flash interface added to the fpga design. I‘m not sure if papilio-prog erase always sectors (64KB) or pages (4KB). The flash chip on the Papilio Pro supports both. Anyway, when I use the flash in the Papilio Pro for own data I always start at 512KB, this is on the save side. Quote Link to comment Share on other sites More sharing options...
LenBiar Posted September 3, 2019 Report Share Posted September 3, 2019 Paraphrase please Here's more info in regards to How do you connect supply lines in Fallout 4 or How can I make money playing video games look into the web-page Quote Link to comment Share on other sites More sharing options...
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