wishbone address bits

[keesj]

Hi,

I am having some issues understanding the wishbone addressing used. I  taking the UART as example

My main question is "what bit is wb_adr_i(2)" in the initial wishbone_in?

https://github.com/GadgetFactory/DesignLab_Examples/blob/master/libraries/ZPUino_Wishbone_Peripherals/COMM_zpuino_wb_UART.vhd#L251

 

100 bits of wishbonne: wishbone_in : in std_logic_vector(100 downto 0);

25? bits of wb_address: signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)

map wishbone bit 3 to???  wb_ard_1 wb_adr_i <= wishbone_in(27 downto 3);

case wb_adr_i(2)   is ?

 

 

 

[keesj]

Having talked with a few people about this I think the code would better be rewritten as
 

signal wb_adr_i: std_logic_vector(23 downto 0);

then case wb_adr_i(0) becomes the first bit

It is possible that the bits 23 downto 19 or contain the  wishbone address?

[Jaxartes]

I would guess the reason for the "downto 2" is that the bus address is in word (32 bit) units while the addresses seen by code are in byte (8 bit) units.  Thus, with "26 downto 2", the numbers of the bits more closely correspond with the processor address space, i.e. wb_adr_i(10) will be byte 1024 (2**10).

At least that's why I did the equivalent in my own 32 bit design.

 

[keesj]

12 hours ago, Jaxartes said:

would guess the reason for the "downto 2" is that the bus address is in word (32 bit) units while the addresses seen by code are in byte (8 bit) units.  Thus, with "26 downto 2", the numbers of the bits more closely correspond with the processor address space, i.e. wb_adr_i(10) will be byte 1024 (2**10).

At least that's why I did the equivalent in my own 32 bit design.

Hi, I can see how this might be useful if you want word aligned memory access indeed. In the example I posted above only a single bit is used to discriminate so I think something else might be going on.

https://github.com/GadgetFactory/DesignLab_Examples/blob/master/libraries/ZPUino_Wishbone_Peripherals/COMM_zpuino_wb_UART.vhd#L251