keesj Posted April 11, 2018 Report Share Posted April 11, 2018 Hi, I am having some issues understanding the wishbone addressing used. I taking the UART as example My main question is "what bit is wb_adr_i(2)" in the initial wishbone_in? https://github.com/GadgetFactory/DesignLab_Examples/blob/master/libraries/ZPUino_Wishbone_Peripherals/COMM_zpuino_wb_UART.vhd#L251 100 bits of wishbonne: wishbone_in : in std_logic_vector(100 downto 0); 25? bits of wb_address: signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits) map wishbone bit 3 to??? wb_ard_1 wb_adr_i <= wishbone_in(27 downto 3); case wb_adr_i(2) is ? Quote Link to comment Share on other sites More sharing options...
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