Why 32MHz XTAL?


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Last night I ported some VGA type Verilog code from an Altera board to my Papilio One. I needed to generate a 65MHz internal clock, but was surprised at the lack of flexibility of the DCM_SP clock generator. I was able to relatively simply generate 64MHz, which was good enough and my old Dell VGA monitor synced correctly, however some of the clock phase controls needed to be tweaked. It occured to me that it might have been better to use a lower frequency reference crystal, such as 10MHz (or even lower if the DCM allows), as it would give more flexibility. I do of course realise that some frequencies will be impossible whatever the reference XTAL. Purely out of curiosity, I wondered why a frequency of 32MHz was selected?

I also tried out adding a PLL to my blink Papilio Pro project, and found the same issue. 65MHz was not possible (only 64 or 66MHz). I checked the Altera project and the PLL was more flexible in that 65MHz was possible.

I have seen some FPGA dev boards which use a programmable frequency chip, rather than a crystal and I can now see why that might be a really useful feature.

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The clocking wizard usually does a pretty good job of getting you close to where you need to be. Please look at this tutorial to see how to use the clocking wizard:


32Mhz was selected because I wanted something below 50Mhz that would be considered low frequency. Also, for the Spartan 3E it had to be over 10Mhz if I remember correctly. I found two reels of 32Mhz oscillators for $10 on eBay and since at the time I was manufacturing all of the Papilio boards on a pick and place in my basement the decision to go with 32Mhz was made easy. :)


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I am sure that there are many cases of people wondering "why did they use that part", and the answer is simply, when they made the design, that part was simply the part that was on hand.

I am pretty familiar with PLLs and the like, and in the case of the DCM_SP with a 32MHz reference, 65MHz is simply not possible. I checked Mouser and replacement xtal osc modules are around £1, so I will likely go this route.

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Try dual-PLL or dual-DCM. These are values for dual PLL on PPro (Spartan6)

Input clk: 32000000.000000Hz, Output clk 95000000.000000Hz

Best result: 96000000.000000Hz, error is 1000000.000000Hz
        PLL Mult=15, Divide=5

Scanning two-PLL approach

Best result: 95000000.000000Hz, error is 0.000000Hz
        Master PLL: Mult=30, Divide=48 (fout=20000000.000000Hz)
        Slave PLL: Mult=38, Divide=8


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