VHDL processes


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Hi everyone,

I have a beginner question about VHDL processes. Let's say, for the sake of argument, I want to synthesize something like a TTL 7400 chip (i.e. quad nand gate). An initial attempt might involve doing something like this:

	process(A1, A2, A3, A4, B1, B2, B3, B4)
		Y1 <= A1 nand B1;
		Y2 <= A2 nand B2;
		Y3 <= A3 nand B3;
		Y4 <= A4 nand B4;
	end process;

It would seem to me that the long dependency list wouldn't make this terribly efficient, at least not during simulation, and that ideally processes should maybe try to do something like this:

	process(A1, B1)
		Y1 <= A1 nand B1;
	end process;
	process(A2, B2)
		Y2 <= A2 nand B2;
	end process;
	// ...etc...

So my first question is "am I correct in my understanding of this?", i.e. is it indeed a good idea in general to separate logic into different processes like this? Or is there some overhead associated with processes that makes it inadvisable for simple cases? And if so, where's the cross-over point?

Or should I forget about focusing so much on simulation and instead concentrate on trying to help synthesis? E.g. something like this...

	-- A, B and Y are now all std_logic_vector(3 downto 0)
	process(A, B)
		Y <= A nand B;	
	end process;

...which technically is the same as my first example above (I think) but would usually wind up in a more efficient circuit (I think)?

I hope these questions aren't too vague, just trying to get my head around best practices. Thanks in advance for any advice and general guidance.

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Basically all your above variants will result in the same circuit on synthesis, because the processes will completely disappear and only the logic equations will remain.

For such simple combinatorial logic the process statement is completely superfluous, you could just write the equations after the begin of your architecture section.

For more complex circuits some hints:

processes must be used for synchronous circuits (which depend on some clock signal as the only signal in the dependency list).

processes can be used for combinatorial circuits (not depending on a clock) when the logic is to complex to be easily written with combinatorical statements. Be aware that the dependency list is a common source of error.

How to organize processes is partly a matter of taste, but some restrictions should be observed:

Every signal can only be set in one process, otherwise it will be a „multi driven net“

Synthesis tools often require specific patterns to „infer“ some logic (e.g. a RAM) from the description. Mixing some custom additional logic into the same process can confuse them.

I usually group together things which belong together. 

For simulation it may depend on the simulator, but I think the total complexity of the circuit is the key factor for computing time, so don’t bother.

To my personal experience the best coding style is the one which allows you to understand your code a year later. This applies to every code in any language not just VHDL.

A usuable (far away from perfect) tutorial for VHDL is the „free range VHDL“ eBook, it is also linked somewhere on Gadgetfactory...



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Thanks Thomas, appreciate the feedback.

In hindsight I shouldn't have used a combinatorial circuit as my example, because my question was meant to be specifically about processes. From your feedback, and what I've seen elsewhere, it sounds like I'm over-thinking things and worrying about issues that aren't as important as I thought they were. And that's fine, because that's also a perfectly valid answer to my question, so thanks again!

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