data_valid pattern?

[keesj]

Hello,

I am starting on my first real project and trying to find a good example of signaling. Many examples I see create a component that does something similar to what is listed bellow
 

in clk
in data[8]
in data_valid
  
  process (clk)
    state machine
      when idle =>
        if data_valid
          change state to blabla
      when blabla =>
        do stuff

Basically a "data_valid" or similar is used to start the process. I am wondering how it normally is prevented that the state machine is not run multiple times(if the signal does not change)

 

 

https://github.com/GadgetFactory/DesignLab_Examples/blob/master/libraries/ZPUino_Wishbone_Peripherals/tx_unit.vhd#L54

or

https://github.com/GadgetFactory/DesignLab_Examples/blob/master/libraries/ZPUino_Wishbone_Peripherals/spi.vhd#L45

and

https://github.com/GadgetFactory/DesignLab_Examples/blob/master/libraries/ZPUino_Wishbone_Peripherals/sid_filters.vhd#L22

 

It there a way to enforce the "data_valid" signal to be low before we start the next iteration or is this somehow not necessary and I am missing something ?

 

[keesj]

FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version (chaper 7.2.4) talks about Interface circuits and using one of the following methods

• A flag FF (Flip Flop)
• A flag FF and a one word buffer
• A Fifo buffer

To solve this problem