anirbax Posted January 9, 2018 Report Share Posted January 9, 2018 Hi, I am trying out the newbie example here: http://papilio.cc/index.php?n=Papilio.GettingStartedISE (plan to load design onto a Papilio One 250) Running synthesis gives this error: Starting Placer Phase 1.1 ERROR:Place:311 - The IOB clk is locked to site IPAD21 in bank 0. This violates the SelectIO banking rules. Other incompatible IOBs may be locked to the same bank, or this IOB may be illegally locked to a Vref site. ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in your design cannot be automatically placed. The constraint file (downloaded from here) NET clk LOC="P89" | IOSTANDARD=LVCMOS25 | PERIOD=31.25ns; When I change the IO type to IOSTANDARD=LVCMOS33, PnR completes without error. What could be the reason why 2.5V CMOS is not supported? Thanks Anirban Quote Link to comment Share on other sites More sharing options...
Thomas Hornschuh Posted January 9, 2018 Report Share Posted January 9, 2018 Hi Anirban, all pins in one so called IO Bank of a Xilinx FPGA share the same Vcc voltage. This means, that you need to assign them a IOSTANDARD with a compatible voltage. So you can for example mix LVTTL (which is 3.3V) and LVCMOS33, but not LVCMOS33 and LVCMOS25. I don't know the details of the Papilio One, but at the Papilio Pro which I use all IOBanks are connected to a 3.3V supply. Why the standard UCF for the Papilo One specifies the clock pin with LVCMOS25 I don't know. Thomas Quote Link to comment Share on other sites More sharing options...
anirbax Posted January 9, 2018 Author Report Share Posted January 9, 2018 I see, that makes sense. Thanks, Thomas. --Anirban Quote Link to comment Share on other sites More sharing options...
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