ISE Placement Error


Recommended Posts


I am trying out the newbie example here:

(plan to load design onto a Papilio One 250)


Running synthesis gives this error:

Starting Placer

Phase 1.1
ERROR:Place:311 - The IOB clk is locked to site IPAD21 in bank 0. This violates the SelectIO banking rules. Other
   incompatible IOBs may be locked to the same bank, or this IOB may be illegally locked to a Vref site.
ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in your design cannot be automatically placed.

The constraint file (downloaded from here)

     NET clk      LOC="P89"  | IOSTANDARD=LVCMOS25 | PERIOD=31.25ns;    

When I change the IO type to IOSTANDARD=LVCMOS33, PnR completes without error.

What could be the reason why 2.5V CMOS is not supported?







Link to comment
Share on other sites

Hi Anirban,

all pins in one so called IO Bank of a Xilinx FPGA share the same Vcc voltage. This means, that you need to assign them a IOSTANDARD with a compatible voltage. So you can for example mix LVTTL (which is 3.3V) and LVCMOS33, but not LVCMOS33 and LVCMOS25. 

I don't know the details of the Papilio One, but at the Papilio Pro which I use all IOBanks are connected to a 3.3V supply. Why the standard UCF for the Papilo One specifies the clock pin with LVCMOS25 I don't know. 




Link to comment
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.

Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.