Rob Bairos Posted November 12, 2017 Report Share Posted November 12, 2017 Hello. Im able to download pre made bitfiles to my Papilio Pro + LogicStart using the bitloader, and DesignLab, however, Im running into a problem trying to create a simple vhdl example from the hamster fpga ebook. Specifically, Im at section 6.4 "Downloading the Design Into the Device." Do I select FPGA or SPI Flash to download to? The screen-shot seems to imply FPGA. At any rate, the Switches_LEDs project fails to operate on the physical board as I expect. Instead when I download to SPI, 3 of the digits show "8" while one is blank. The LEDs are all off, and the switches have no effect. I did make the following changes from the tutorial for the Pro board: I set device to Spartan6 xc6slx9 tqg144 speed -2 And the constraints file is: # Constraints for Papilio Pro NET switch_1 LOC = "P120" | IOSTANDARD=LVTTL; ; #pap1 was switch (6) p3 NET switch_0 LOC = "P121" | IOSTANDARD=LVTTL; #pap1 was switch(7) p4 NET LED_1 LOC = "P133" | IOSTANDARD=LVTTL; #pap1 was led(6) p16 NET LED_0 LOC = "P134" | IOSTANDARD=LVTTL; #pap1 was led(7) p17 Above changes based on pinout chart: http://papilio.cc/index.php?n=Playground.PapilioPinouts Bit stuck for ideas, any help appreciated. Thanks. Quote Link to comment Share on other sites More sharing options...
Rob Bairos Posted November 12, 2017 Author Report Share Posted November 12, 2017 Okay the first line of my ucf file I had:NET switch_1 LOC = "P120" | IOSTANDARD=LVTTL; ; #pap1 was switch (6) p3 instead of NET switch_1 LOC = "P120" | IOSTANDARD=LVTTL; #pap1 was switch (6) p3 The double "; ;" was causing a syntax error I didn't notice. I was actually downloading the previous bit file unknowingly. Downloading to SPI Flash, leaves everything working! -Rob Quote Link to comment Share on other sites More sharing options...
Jack Gassett Posted November 12, 2017 Report Share Posted November 12, 2017 Excellent, glad you got that sorted out too. BTW, I'm working on new papilio pro examples over at gitlab. I've still got a long way to go but it might be interesting to see what you think. https://gitlab.com/Papilio-FPGA/papilio-quickstart-vhdl I've also put together a cloud environment so you don't have to mess around with installing Xilinx ISE to synthesize these new projects. You will need to place your Xilinx.lic file in ~/.Xilinx/Xilinx.lic for it to work. Keep in mind this is all just tests that I'm running, not really ready for prime time yet. But might be worth checking out if you are interested. https://codenvy.io/f?id=factoryyd01z6lgdawlk52f Jack Quote Link to comment Share on other sites More sharing options...
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