SUMP Logic analyzer not responding

[keesj]

Hi,

Yesterday I started playing with the sump logic analyzer code on the Papilio Pro. I took the basic example and started modifying the system to add an additional serial port and started sniffing that serial port. In my sketch I added some serial.write and everything works as expected until I start writing 4 bytes to the serial e.g  not "kee" but "kees". At that point OLS no longer works.

any hints what is going on? In the attached picture you can see that the serial.write actually takes some time from the CPU to execute is this blocking the wishbone bus or something similar causing the Logic analyzer to stop working? I am using ols-0.9.7.2.

My goal is to be able to "trigger" on a certain UART character or other events on the system. I plan on glueing the SUMP with the UART or other blocks. Is the current code in the IDE the best one to follow or should I base the code on the new whishbone based interface?.

I have had more little problems:

• In OLS I can not configure the system to use 1 bank e.g. 8 bits as the SUMP code currently always sends 16 bits/2 bytes
• I would be interested in accessing the SUMP data over a different port from the UART (possibly JTAG or a different port) but the jtagserver is not ported to linux
• It looks like RLE is not working (kinda documented but not very clear what the status is)

 

[Jack Gassett]

On 10/11/2017 at 1:15 AM, keesj said:

Hi,

Yesterday I started playing with the sump logic analyzer code on the Papilio Pro. I took the basic example and started modifying the system to add an additional serial port and started sniffing that serial port. In my sketch I added some serial.write and everything works as expected until I start writing 4 bytes to the serial e.g  not "kee" but "kees". At that point OLS no longer works.

What is the behavior when it stops working? More details could help me give you better advice. You might try doubling your sample rate, maybe it not working is just that the sample rate is not high enough? 

On 10/11/2017 at 1:15 AM, keesj said:

any hints what is going on? In the attached picture you can see that the serial.write actually takes some time from the CPU to execute is this blocking the wishbone bus or something similar causing the Logic analyzer to stop working? I am using ols-0.9.7.2.

My goal is to be able to "trigger" on a certain UART character or other events on the system. I plan on glueing the SUMP with the UART or other blocks. Is the current code in the IDE the best one to follow or should I base the code on the new whishbone based interface?.

When I test the SUMP core the main things I do is have the serial port send out the ascii table and then make sure that I can capture it. I'm almost 100% certain I did this with the SUMP core in the example you are using... But it's been a while so I don't remember exactly.

The example in DesignLab should be the best one to work off, definitely don't use the wishbone interface one, that is not even close to being ready.

On 10/11/2017 at 1:15 AM, keesj said:

I have had more little problems:

• In OLS I can not configure the system to use 1 bank e.g. 8 bits as the SUMP code currently always sends 16 bits/2 bytes
• I would be interested in accessing the SUMP data over a different port from the UART (possibly JTAG or a different port) but the jtagserver is not ported to linux
• It looks like RLE is not working (kinda documented but not very clear what the status is)

 

jtagserver should be easy to port to linux, its a cygwin app under windows if I remember correctly. I just never had the time (and no one showed interest) to make any little changes needed to work under linux. 

Jack

[bnusbick]

Try making channel 2 always high and see if OLS still stops working.

Blake

[keesj]

15 hours ago, Jack Gassett said:

What is the behavior when it stops working?

Well the behavior is that the capture never completes. One small modification I did that appeared to improve a little was replacing the if(serial.available) by while(serial.available). I will perform more tests(also try @bnusbick's suggestion.