keesj Posted October 11, 2017 Report Share Posted October 11, 2017 Hi, Yesterday I started playing with the sump logic analyzer code on the Papilio Pro. I took the basic example and started modifying the system to add an additional serial port and started sniffing that serial port. In my sketch I added some serial.write and everything works as expected until I start writing 4 bytes to the serial e.g not "kee" but "kees". At that point OLS no longer works. any hints what is going on? In the attached picture you can see that the serial.write actually takes some time from the CPU to execute is this blocking the wishbone bus or something similar causing the Logic analyzer to stop working? I am using ols-0.9.7.2. My goal is to be able to "trigger" on a certain UART character or other events on the system. I plan on glueing the SUMP with the UART or other blocks. Is the current code in the IDE the best one to follow or should I base the code on the new whishbone based interface?. I have had more little problems: In OLS I can not configure the system to use 1 bank e.g. 8 bits as the SUMP code currently always sends 16 bits/2 bytes I would be interested in accessing the SUMP data over a different port from the UART (possibly JTAG or a different port) but the jtagserver is not ported to linux It looks like RLE is not working (kinda documented but not very clear what the status is) Quote Link to comment Share on other sites More sharing options...
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