Reset behaviour question

Brad Robinson

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Hey All,

I've got a problem with a design I'm working on for Papilio Duo as follows:

  • Programming SPI flash works fine and starts up correctly on every power on.
  • After power on if I program the FPGA directly there's some randomness in whether it starts correctly.  Usually it fails. Basically the Z80 code executes in a way that can "never happen".  Either the T80 core isn't getting reset correctly or there's some issues with ram/rom. It looks like a CALL instruction is simply skipped.
  • After programing to FPGA, using the reset button on the classic computing shield resets correctly - everytime.

So... I'm wondering if there's something different about the reset procedure after programming directly to FPGA vs programming to SPI Flash using the reset button.

I'm sure this is an issue in my design, but not really sure what to look for - any hints greatly appreciated.


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OK, so I figured this out... silly amateur mistake on my part.

For the record, the problem was caused by using synchronous resets and also connecting the reset signal to the coregen'd clock core.  This of course caused the clock core to stop and therefore parts of the design weren't getting the reset (synchronous reset won't reset without running clock).

Interestingly the slower clock circuits were getting reset while the faster ones weren't. 

Anyway, lesson learned. :)


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Synchronous resets are not an issue. Reseting the clock generator is :)

General rule is:
  - If you have a single clock on your system, make sure the reset signal is deasserted at least one clock cycle after your clocking is stable. Do not deassert it if you use a DCM/PLL until it locks. Do not reset DCM/PLL unless you absolutely need to.
 - For multiple clocks its a bit more tricky. You will need a reset for each of your clock domains. Here async reset for the reset itself may prove useful - assert resets asynchronously, but deassert them synchronously for each of your clock domains. May not be enough, though.


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  • 2 weeks later...

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