RAM device / timings for small VGA project


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For a personal hobby project I'm looking to make a small vga display using an fpga. I was thinking of making the display 640x480 pixels with one byte colour per pixel at 60hz (I believe those timings should work on any monitor?)

By my calculation that means I need to read 640*480*60 bytes from the ram every second which is 18432000 bytes per second giving a time per byte of a little over 54ns per pixel.

I'm looking at a device something like this for my memory.


The datasheet indicates that it has an access time of 45ns so by my understanding it should be fast enough for my fpga to read the data from it. But I'd have to update it during the period when no data is being displayed as it's not fast enough to complete a read and write in that time.

Are my calculations correct, and would such a device be suitable for using in this way? Or did I miss something?

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We have such an implementation using the SDRAM. If I recall well, it works OK at 640x480x8bit.
Ideally you should get a memory which is almost 3 times as fast as the fastest datastream you need (read or write). You will also need to arbiter between the read and write requests, and probably will need a read FIFO to account for the jitter of the arbiter (we do exactly that).

You may want to take a look here: https://github.com/alvieboy/ZPUino-HDL/blob/master/zpu/hdl/zpuino/devices/video/vga_generic.vhd


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Regarding video timings, the pixel rate is generally higher than the calculation of refresh*horizontal*vertical, due to periods that no pixels are being transferred.  For the most common 640x480x60Hz resolution, it's 40ns per pixel instead of 54ns. http://tinyvga.com/vga-timing has more detail.

One way to stretch that time is to buffer part of the screen in the FPGA's own on-chip memory.  If you read and buffer one scan line at a time, you can get it to 50ns per byte, using only 640 bytes of buffer memory.  (Calcuation: 640 pixels in a scan line, one byte per pixel, a buffer to hold one scan line is 640 bytes; in the standard 640x480 screen, a scan line takes 32us; 32us/640=50ns.)

If you can reduce the amount of memory your screen image takes up, you might be able to fit it entirely onto the FPGA without any off-FPGA RAM.  That gives you a number of benefits: It's easy to work with, it's fast, and (at least on the ones I've used) it's dual-ported.  The downside is that capacity is limited (it depends on the particular FPGA).  But you may be able to reduce how much you need, using techniques from back when computers' memory was much smaller:  Fewer bits per pixel; text mode / tile mapped graphics.  (For example, 1024x768x8bpp would be 768kB, but https://github.com/Jaxartes/fpga_robots_game/ gets 1024x768 resolution with only 12kB RAM for video.)

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