OV7670 vhdl code.


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So you're trying to port this to an Altera FPGA?

Of course, the easier way would be to make it work first on the original hardware. Then port it.

If I had to debug this design, what I would do first check for valid HSYNC and VSYNC. Does the monitor recognize the frame timing?
With valid sync signals applied, connecting any color signal e.g. VGA_greeen to 3.3 V should result in a bright (e.g. green) screen. When this works, we know the basic clocks are correct. DISCLAIMER: My monitor does not turn into a fireball when I do this but I don't know about yours.

But as said, porting a design without reference on working hardware is an uphill battle. Besides simulating, maybe it's a good time to buy a Papilio Pro as a logic analyzer :) which might be part of the 2nd step I'd do.

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