Newbie - Problems creating working designs with ISE Schematic


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I am new to FPGA design (but an experienced electronics engineer). I am learning how to create simple designs on a Papilio One 500k with ISE schematics. I am familier with basic logic design, and so far I have created some simple combinational logic and a divider chain to produce a 10Hz clock. This works fine, but when after editing and add more bits on, the existing parts no longer function properly. The frustrating thing is that the schematics look correct, but they do not function as expected on the FPGA. After searcing the internet for answers, I suspect it might be something to do with net names or constraints, but that's as far as I have got. Can anyone point me in the right direction (I cannot be the only beginner have these problems!)? By the way, I am aware there are limitations in using schematics (compared with using Verilog or VHDL). I am developing this project for my college students and there will be insufficient time for them to learn an HDL, although I will of course give them an introduction to the subject. Many thanks for reading this.

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Some miscellaneous tips; know that I'm not very advanced at this (I've been doing FPGA designs for two years, but only as a Saturday afternoon hobby).

  • Using logic output as a clock is not recommended on FPGAs.  I'm not up on what can go wrong with it, but I believe the routing for the two kinds of signals is different.  Glitches (false edges produced by the logic) might be a problem too.  Two alternatives are:
    • Use one of the on-chip PLLs to convert the 32MHz clock to another speed (but 10Hz might be way out of its range).
    • Use the higher speed clock (32MHz) and control the speed of your logic by applying a "clock enable" signal to every flip-flop.  The clock enable is a synchronous signal, with 10 pulses per second, 1 clock cycle per pulse.  That's is what I'd recommend here.
  • Net names have to get mapped to the pins on the FPGA.  Generally the constraints file (which in ISE is a UCF file) controls this.  If your constraints file is missing or absent or ISE is not set to use it, you might have problems.  (I don't know what exact problems they are.) You can find out what pin is used for what.  It's in the GUI as "Pinout Report", or in a file named projectname_pad.txt.  The first two columns are pin number and net name.
  • Look for warning messages from the build tools.  These give so very many warnings that it's a nuisance, and I often ignore them, but when something stops working, they might tell you something.  The GUI can show them to you, or they appear in various output files.  Some filename suffixes are: .syr, .par, .map, .bgn, .drc.
  • ISE contains a simulator.  If you can get that to work, it could show you what's going on inside your design.  I haven't used it, so can't give many pointers, except I think you probably want to not use the 10Hz divided-down clock with it, it'll take too much time.
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Hello Laurence,

Can you post a screenshot of your schematic and maybe even your whole project so we can get a better idea of where the problem might be?

Also, please take a look at DesignLab as it is schematic based and hides some of the complexity of creating a new project in ISE by taking care of the project settings, ucf file, etc.

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Hi Laurence,

when you approach FPGAs with a general electronics background, there may be quite many surprises. Time has moved on.
FPGAs are meant to be programmed following the "synchronous design" paradigm where small chunks of combinational logic are glued together by clocked registers. Deviate from that at your own peril.

Don't try to build memory elements (flipflops) from gates as in a textbook. If that's what you're trying (not sure), the FPGA isn't meant to be used this way

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  • 4 weeks later...

Thanks guys for your suggestions. The particular problem I had seemed to be caused by clocking a counter from a logic gate fed from outputs of another counter, i.e. to create a particular division ratio. It worked okay until I modified a different part of the design. I suspect that the width of the clock pulse was marginal and so it stopped working when the FPGA was re-routed. I fixed it by clocking the counter directly from another counter output, i.e. a longer pulse. I am not making flip-flops from gates. Agreed, I am sure it is not a good idea to drive clock inputs from combinational logic. I have noticed that ISE warns about this when doing the synthesis. I can see that driving the counter clocks from the system clock would get around this. This then drives us down the synchronous design route. I have not done a lot of real digital design in the past 20 years so I agree that I am a bit out of touch with the design methods used in programmable logic. There is plenty to learn! Thanks again for all of your advice.

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