Interfacing with VHDL circuit with ZPUino


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Dear Altruists,

I'm new to Papilio Pro FPGA. I designed my  circuit with VHDL and also synthesized it, and it is ready to be loaded in the papilio pro fpga. My circuits interface has an input of 64 bits and output of 1 bit. I need only to send this 64 bit data from my pc to FPGA and receive the output of 1 bit ( please check the uploaded circuit interface). I already watched most of the learning videos. I have already contacted Mr. Alvie and thanks to him he reply with an answer, but it was a little difficult for me to understand as I am new to FPGA.  His answer was that I should connect my circuits to one of wishbone ZPUino slots, and use ZPUino to interface with the USB/serial using software moving data to and form my circuits. However, the things that I don't understand are that:


1. Should i connect my circuits to wishbone bridge  and then connect my circuits to the wishbone slots as you did here ( If  the answer yes, should I connect the the both input and output to the wishbone bridge. If answer no, then should I interface my circuits directly to the ZPUino wishbone slots. 

2. If I connect my circuits to ZPUino wishbone slots. The input 64 bits and the output 1 bit should be connected to what to the slots or Paplilio Pro Pins. 

3.  Mr. Jack illustrate in the learning site videos that ZPUino should be loaded to the SPI not to the FPGA Spartan6. So, If I am going to interface my design to ZPUino how can I load the circuits to the FPGA. 

4. If I am going to make an interface of the UART I think I just need to follow as same as Mr. Jack did in this video( )


Please forgive my shortcomings. I am new to these things. Any help will be highly appreciated. 




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  • 2 weeks later...

Hello and sorry for the slow response,

Yes, you will want to follow this tutorial:

You will be making 1 Wishbone peripheral but in the part where you setup the Wishbone registers you will want to use two of the registers for your 64 bit input. So in the Wishbone_to_Registers_x10 symbol you will use register0_out(31:0) and register1_out(31:0) to capture your 64 bit input into your own VHDL code. In your sketch you will write a 64bit value into the two 32 bit wishbone registers (0 and 1) which will then be available to your code at the register0_out(31:0) and register1_out(31:0) ports. 

Hope that helps,


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  • 1 year later...

Here's an example of one of the broken URLs you asked for, Jack.

If you use the formula which normally works, moving learn into the domain name, and deleting it from the path, this one still gets a 404.

What happened to this tutorial? As I recall, it was good! As I mentioned, I figured out how to do it in a basic ZPUino SOC sketch without any library, so converting it to a library would make for a nice example of something substantial connected to a sketch via wishbone, in addition to your existing examples.

Cheers, Joe


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