Laurence Posted August 29, 2016 Report Share Posted August 29, 2016 Hi, I am new to this forum. I am running a course on logic design and I want to include a practical introduction to FPGAs. I am considering Papilio as the platform to use as there will not be time to learn VHDL or Verilog. My students are already used to using schematic design tools such as Proteus. We are using Windows 10. Is Papilio the right solution? I understand that Xilinx have superseded ISE with Vivado (which is more complicated and does not allow schematic entry). How does this affect Papilio and DesignLab? Many thanks. Quote Link to comment Share on other sites More sharing options...
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