offroad Posted August 1, 2016 Report Share Posted August 1, 2016 Hi, is it possible that the usb_cts and usb_rts nets in the pipistrello.ucf constraint file are mixed up? In my opinion, the following should be correct: #NET "usb_cts" LOC = "A9" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; // SWITCHED WITH RTS -mn #NET "usb_rts" LOC = "C10" | IOSTANDARD = LVTTL | PULLUP; // SWITCHED WITH CTS -mn Schematic: RTS# = pin 40 on U7 = D2 = C10 on FPGA CTS# = pin 41 on U7 = D3 = A9 on FPGA In my understanding (please correct if wrong) CTS serves double duty on the FTDI chip: - Setting 1'b1 (which mean "not clear to send") blocks incoming traffic from USB. - Any level change kicks off the current 62+2 byte package over USB without waiting for the latency timer. I did an experiment with existing code where triggering a pulse on CTS decreased the roundtrip time (for two "rounds") from 4.00 to 3.75 ms, a small but measurable improvement. Quote Link to comment Share on other sites More sharing options...
Join the conversation
You can post now and register later. If you have an account, sign in now to post with your account.