Pipistrello .ucf file: RTS/CTS mixed up?


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is it possible that the usb_cts and usb_rts nets in the pipistrello.ucf constraint file are mixed up?

In my opinion, the following should be correct:

#NET "usb_cts"        LOC = "A9"   | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; // SWITCHED WITH RTS -mn
#NET "usb_rts"        LOC = "C10"  | IOSTANDARD = LVTTL | PULLUP;                   // SWITCHED WITH CTS -mn

RTS# = pin 40 on U7 = D2 = C10 on FPGA
CTS# = pin 41 on U7 = D3 = A9 on FPGA

In my understanding (please correct if wrong) CTS serves double duty on the FTDI chip:
- Setting 1'b1 (which mean "not clear to send") blocks incoming traffic from USB.
- Any level change kicks off the current 62+2 byte package over USB without waiting for the latency timer.

I did an experiment with existing code where triggering a pulse on CTS decreased the roundtrip time (for two "rounds") from 4.00 to 3.75 ms, a small but measurable improvement.


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  • 6 months later...

Stumbling over my old post, if someone is sent here by Google on a mission to reduce latency...

The secret to achieving low latency with a UART is... don't use a UART.
The 2232H chip, programmed through the DLL interface, can achieve physical roundtrip (!) times, e.g. send a byte via JTAG bypass through the FPGA and back in MPSSE mode, of slightly over 1/8 ms.
If I extrapolate the 3.75 ms UART roundtrip time I achieved earlier... my boss wouldn't be happy :-)

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