shahabamo Posted May 28, 2016 Report Share Posted May 28, 2016 Hi, I am trying to use ZPUino on my own custom board. I've picked ZPUino_Papilio_DUO blackbox, created a top level module accordingly and finally modified the .UCF file. As my board has a 24 MHz crystal oscillator, I instantiated a DCM block and converted 24MHz to 32MHz and fed the clk_32 signal (output of DCM) to ZPUino_Papilio_DUO_blackbox. After a successful synthesize, In the Translate step I got the following error: logical net 'XLXI_82/clk_32' has multiple driver(s): pin CLKFX on block XLXI_82/inst_clk_24to32/dcm_clkgen_inst with type DCM_CLKGEN, pin PAD on block XLXI_82/clk_32 with type PAD I also disabled the BUFG on DCM to see if this is the source of error, but still no chance! any help is appreciated. Quote Link to comment Share on other sites More sharing options...
Jack Gassett Posted May 31, 2016 Report Share Posted May 31, 2016 Hello, It is going to be a matter of getting the Buffers setup right, you might want to keep experimenting with different options or read the Xilinx Clocking Guide for Spartan6. Or, maybe the easiest thing, the clock should already be coming into a DCM/PLL, just change the settings of that to a 24Mhz oscillator instead of 32Mhz. Then the buffers should all be setup correctly. Jack. Quote Link to comment Share on other sites More sharing options...
shahabamo Posted June 1, 2016 Author Report Share Posted June 1, 2016 Thank you Jack, As you mentioned correctly, the Buffers lining-up in series was causing this problem. I removed the extra DCM and modified the PLL coefficients in previous clkgen module and the problem wiped out! Regards. Quote Link to comment Share on other sites More sharing options...
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