TFT 3.2" SSD1289 Controller IP

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I am trying to write HDL driver for the papilioDuo to interface with the TFT 3.2'' SSD1289 from sainsmart, (parallel dirver).

I have been following initialization FSM from the datasheet of the SSD1289, but I have not being able to make progress so far (screen is always blank).

Are there any plans to support a TFT papilio wing?

Has someone already verilog/vhdl to drive the SSD1289, or are there any tips you can provide? 



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Hi Jack,


Thank you very much for the quick reply!

I am not using an existing CPU core for the Papilio, but instead I have created my own version of a modified Z80.

I am currently not planning on using the Arduino that comes as part of the papilioDuo board, since I believe it might impact the frame-rate .

I am working on a GameBoy classic clone, (all from scratch RTL, no existing CPU), and I would like to have my own LCD driver for the task.

I have already some Verilog code that attempts to connect with the SSD1289, however I can't make it to display any colors.

I was planning on using a logic analyser to capture the first few milliseconds of a working ArduinoMega LCD initialization routine, using the UTFT C++ Arduino libraries from Henning Karlsen, and then try to see how far off my controller is from the reference waveforms.  

I was wondering if there was a pre-existing opensource HDL core to drive the SSD1289 from the Spartan6, or some tip on to make this little monster it work.

Getting my hands on a logic analyser has proved a difficult task far :(, I can't still figure out the correct frequency to interface with the SSD1289 (I am guessing some where between 16Mhz < f < 32Mhz should work).


Thanks again for your help, and by the way your Papilio boards rocks!




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Thank you for the words of encouragement about the Papilio. :)

It is possible to use the Papilio as a Logic Analzyer:


Also, you can embed a Logic Analyzer into the ZPUino design using DesignLab, so theoretically you could run the UTFT Arduino Libraries from Henning Karlsen on the ZPUino and also capture the waveforms with an embedded Logic Analyzer.



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