implementing a new wishbone slot

[sky_moo]

I would like to implement a ZPU wishbone slot for an i2s receiver/transmitter using the open core project I2S Interface (http://opencores.org/project,i2s_interface) 

This opencore I2S component is already implemented as a wishbone peripheral and requires an input signal called "wb_sel_i" / "wishbone input select" which I am not certain how this should be wired up to the 100 bit wishbone input signal on the ZPU. In some projects it is referred to as a 4 bit bus:  input [3:0] wbs_sel_i,

Where can I find more information about what input and output signals are available from the wishbone bus? Is there a good resource where I can learn about the wishbone protocol?

I am using papilio duo. I am fairly new to FPGAs but am learning quickly. 

Thanks.

[alvieboy]

Hi,

I just took a quick look, and that "sel" signal is only one bit wide, and must be tied to '1'. That signal does not make sense at all - the SEL signal is used for byte-access, which the device does not support (ZPUino also does not support it for devices).

This design also uses CTI and BTE. You should hardcode them to all zeroes.

Regarding documentation, you have the official Wishbone doc, but its a bit hard to follow...

Alvie

[sky_moo]

Ok. Thanks alvie, thats good information... If I get it working I'll share it on github... now - time to fix the vhdl and connect the PCM5102A DAC.... @ 384kHz and 32bps....