breakin Posted March 23, 2016 Report Share Posted March 23, 2016 Hi, I'm writing a serial SRAM-interface between AVR and the SRAM available to the FPGA. Aim is to learn VHDL/FPGA programming so I'm not taking easiest route here. But I have a problem! I now have a small program on the AVR-side that transmits ones and zeroes to the fpga at a very low rate (say one per second now during debug). I'm using the MOSI-pin for this. When switching from 0 to 1 I detect _one_ rising edge on the fpga (by tracking value from last clock and current clock and looking for a 0->1 transition). When switching from 1 to 0 I detect _multiple_ rising edges on the fpga. There should be none. My question is if the AVR outputs correct nice digital signals that are interpreted as ones and zeros on the fpga, or do I need to process them somehow? Is there something special about the MOSI pin? All my VHDL programs looks fine during simulation so now I'm looking at other external factors. My VHDL program is still under suspicion of course! Thanksful for any help I can get! Quote Link to comment Share on other sites More sharing options...
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