Data tranfer via USB on Papilio One


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I wanted to transfer data via the FTDI chip channel B to the computer. I used verilog and wrote a code which simulates fine. The baud rat was set to 9600 in the verilog code. But i am unable to get any data through. The connection itself sometimes get lost. Also i can see only two pins rx and tx connected to the ftdi chip so how do i set the transfer rate for this process


Urgent help needed. 

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You set the baud rate on the host (PC) side, in whatever program you're using to communicate with the FPGA.


You're right, there are only two pins which communicate the data between the FPGA and the FTDI chip.  The transfer rate isn't communicated -- it's set independently on each side.  They have to be set to the same value (within a few percent) in order to communicate.


On the FPGA side, this is something you do in your Verilog code, usually with some kind of counter.  On the other side, it's controlled by the host (PC).  I imagine the host sets up the baud rate on the FTDI chip over USB.  Anyway, that's taken care of in the operating system and device drivers.  Those in turn are set up by whatever communication software you run on the PC side.


The exact details of that depend on the communication software and the operating system.

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Yes you right, I have designed the counter for a baud rate of 9600 and data is sent over at those specific intervals. I read somewhere that the baud rate must be 3 times the required value. Is that necessary. And even after I gave the required 9600 baud i coudnt get any values in the compuetr, I used coolterm to view the values. also We need to connect to serail transmitter B right?

Help need with code. I am attaching the code written in verilog please review it for mistakes.



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I'm sorry but your code makes no sense at all, it's not even remotely close to anything working.  It has so many problems that I'm not even sure where to begin.

In general, it's probably a good idea to pick up a book about Verilog or VHDL and try some of the examples before you dive in and write your own code.


OK, lets just mention some of the worst things.  I will just talk about the module USB_PC to limit the amount of writing

1) You are trying to use a for loop to to send out data.  In Verilog, for loops are used to generate logic, not generate data. (You are not writing C code.)  You need to have a shift register that you load with the transmit data and shift out one bit at a time for each baud rate clock.

2) You need to generate a start bit, then the 8 bits of data output, and finally a stop bit.  You are just (constantly) sending out the 8 bits of input data.

3) There is no input to the module that tells it to send out one byte.  You should probably also have a busy output so that the top level module knows when it can send out another byte.

4) You write always @(baud), this is how you normally generate combinatorial logic and not sequential logic (like flip-flops) that you would need for a shift register.


You might want to take a look at this project:

It's a simple project with a receive UART, memory to store the receive data, and a transmit UART.  The receive data will be stored in memory until it receives a CR (hex 0d) then all the data received since the last CR will be transmitted out.  The project is for Pipistrello so you need to modify the ucf file for Papilio and change the input clock frequency parameter from 50 MHz to 32 MHz.



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