DesignLab 1.0.7 and Papilio One

[gremplar]

OK, I have an old Papilio One that I am bent on using as a cheap logic analyzer.

 

I hooked it up, via USB, started DesignLab 1.0.7, and had issues with downloading the bit file for the OLS component, but plugging and unplugging seemes to eventually have made it work:

 

Programming External Flash Memory with "C:\DesignLab-1.0.7\tools/logicanalyzers/500K/Sump_Logic_Analyzer_P1_500K_2.12.bit".
Found SST Flash (Pages=2048, Page Size=264 bytes, 4325376 bits).
Erasing    :
Ok
Verifying  :
.....Pass
Programming :
..............Finished Programming
Ok
Verifying  :
Using devlist.txt
.....Pass
Done.
SPI execution time 5909.2 ms
USB transactions: Write 2882 read 2165 retries 0
JTAG chainpos: 0 Device IDCODE = 0x41c22093    Desc: XC3S500E
Using devlist.txt

ISC_Done       = 0
ISC_Enabled    = 0
House Cleaning = 1
DONE           = 0

 

From looking at the above results, I think I can reasonably conclude that it programmed the flash OK and that the FTDI serial interface is working.

 

Problem is, when the UI for OLS comes up, I cannot seem to get it to connect to the Papilio One.  COM6 and COM7 are reported in Device Manager, and since COM7 is the FTDI chip, I am assuming that COM6 is what I want to use.

 

Selecting COM6 and any of the baud rates from 115200 down to 38400 all fail, with no device detected.  Trying COM7 doesn't work either.

 

So, any hints on how to debug this?  Do I have a bad board and just need to bin it?

 

Thanks,

Jim

[Felix]

what commandline did you use?

 

also after programming it, follow it with

 

"papilio-prog -vc"

[Jack Gassett]

Hello Jim,

 

You will want to use the second COM port so COM7 is what you will want to use and you want to use a speed of 115200. 

 

Let us know if those settings help out.

 

Jack.