terryphi Posted November 23, 2015 Report Share Posted November 23, 2015 Hi There, I know 'can you please debug code' posts are generally frowned upon, but I'm having a bit of trouble with what, I think, should be a trivial problem. What I'm trying to do is connect the 32 Mhz clock pin to a counter as well as a DCM, but when I do this, I get the error"Port <CLK> has illegal connections. This port is connected to an input buffer and other components." When I hook the counter or DCM up separate, there is no issue. Can I only have the clock signal going to one location? Is there some sort of signal divider? My main VHDL file is as follows:ibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity main is Port ( LED : out STD_LOGIC_VECTOR (7 downto 0); SWITCH : in STD_LOGIC_VECTOR (7 downto 0); CLK : in STD_LOGIC); end main;architecture Behavioral of main issignal counter : STD_LOGIC_VECTOR(29 downto 0);COMPONENT cnt PORT( clock : IN std_logic; total : OUT std_logic_vector(29 downto 0) );END COMPONENT; COMPONENT dcm2 PORT( CLKIN_IN : IN std_logic; CLKFX_OUT : OUT std_logic; CLKIN_IBUFG_OUT : OUT std_logic; CLK0_OUT : OUT std_logic ); END COMPONENT;begin Inst_dcm2: dcm2 PORT MAP( CLKIN_IN => CLK, CLKFX_OUT => open, CLKIN_IBUFG_OUT => open, CLK0_OUT => open ); Inst_cnt: cnt PORT MAP( clock => CLK, total => counter );LED <= COUNTER(29 downto 22);end Behavioral;The counter code is:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity cnt is Port ( clock : in STD_LOGIC; total : out STD_LOGIC_VECTOR (29 downto 0));end cnt;architecture Behavioral of cnt issignal counter : STD_LOGIC_VECTOR(29 downto 0);beginclkProc : process(clock)begin if rising_edge(clock) then counter <= counter+5; end if; total <= counter;end process;end Behavioral;and the DCM setup is: Quote Link to comment Share on other sites More sharing options...
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