sasadoesblub Posted October 29, 2015 Report Share Posted October 29, 2015 Why hello there,working on FPGAs for my thesis, atm looking into remote configuration. Am I right in the assumption (based on the schematics) that there is no connection between the atmega and the flash on the board and hence I cannot use the mc to access the memory? Also I don't see any connection between the mc and the fpga which would allow me to configure the fpga directly from the mc. Is the "only" way to configure it by writing from the ftdi to either the fpga or flash? Thanks for your time,cheers Quote Link to comment Share on other sites More sharing options...
offroad Posted October 29, 2015 Report Share Posted October 29, 2015 Hi, I don't have the schematics in front of me, but couldn't I implement such a bridge on the FPGA fabric? Quote Link to comment Share on other sites More sharing options...
Jack Gassett Posted October 31, 2015 Report Share Posted October 31, 2015 Hello, It should be very easy to make a circuit on the FPGA that connects the SPI Flash pins to any of the pins on the AVR chip. You can look at these two projects for a general idea of how to do this: http://gadgetfactory.net/learn/2014/08/29/papilio-duo-program-arduino-bootloader-using-happyjtag2/http://gadgetfactory.net/learn/2014/08/28/papilio-duo-program-with-avr-dragon/ As far as programming FPGA from AVR, your best bet is to load a bit file to the SPI Flash to accomplish that task. Should be very doable. Jack. Quote Link to comment Share on other sites More sharing options...
sasadoesblub Posted November 2, 2015 Author Report Share Posted November 2, 2015 Thanks for your responses so far! As far as programming FPGA from AVR, your best bet is to load a bit file to the SPI Flash to accomplish that task. Should be very doable.This implies that the FPGA itself is used as a bridge right? So every configuration needs to have the connections setup on the fpga to program the fpga itself? That might conflict with my needs.. Quote Link to comment Share on other sites More sharing options...
Jack Gassett Posted November 2, 2015 Report Share Posted November 2, 2015 Maybe you can describe what you need to do so we can help with the best solution? Jack. Quote Link to comment Share on other sites More sharing options...
offroad Posted November 3, 2015 Report Share Posted November 3, 2015 BTW, are you familiar with "the" default startup process of a Xilinx FPGA, given a SPI flash in its gravity well?See 2nd post here:http://forum.gadgetfactory.net/index.php?/topic/1932-how-does-the-spi-flash-auto-configure-the-fpga/ Quote Link to comment Share on other sites More sharing options...
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