Platform for use with GHDL

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Could someone recommend which Papilio board and shields/wings would be good for learning VHDL/GHDL. This is to help visualize work for a college course that uses GHDL and GTKWave to teach basic digital logic.


I was thinking that having an actual board (in addition to using GHDL and GTKWave) would help to learn VHDL/GHDL basics.


I have used the Arduino Uno before and I like what I have seen of the software that is used for the Papilio Duo, but I'm not sure if this is the best board to use with VHDL/GHDL and also I'm wondering which shields/wings work well with a board for learning VHDL as well.


Thanks for any guidance.

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I'm not familiar with GHDL but any of the Papilio boards are good platforms for learning VHDL. I suspect you would be well served by a Papilio One 500K combined with the Logicstart megawing. It's a bit lacking in peripherals compared to many of the commercial FPGA development boards out there but there's a lot you can do with it and it's a compact and very reasonably priced package.


For basic digital logic you could probably get by with a low cost CPLD but the FPGA is nice in that it's a lot more capable and has onboard memory that can function as ROM or RAM, PLL clock generators and other fancy features.

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if the plan is to teach "basic digital logic", not VHDL, you could have a look at Verilog instead. Less bloated.


A five-line example speaks for itself:

module hello (input clk, input sw1, input sw2, output LED1, output reg LED2, output reg LED3);

    assign LED1 = sw1 & sw2;     // example combinational logic = blocking assignment

    always @(posedge clk) begin  // example registered logic <= non-blocking assignment

        LED2 <= sw1 ^ sw2; 

        LED3 <= sw1 | sw2;




For added value, it comes with one major bug (not syntax) that is guaranteed to sink the boat in a real-world application even though it seems to work just fine.

However, finding that is left as an exercise to the student (/instructor) :)

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I don't think "bloated" is the right term here. The verbosity of the code has absolutely no relation to the resulting implementation in the FPGA, you can describe the same circuit in either language with the same result. "Bloated" code suggests sloppy convoluted code that results in a program that consumes a lot of resources and performs poorly, but that's not how it works with HDL. As long as you describe the circuit you want accurately, everything un-needed gets optimized out.


Personally I like VHDL much better because it's so much clearer what is going on. Verilog does allow for more compact statements, but so what? I can type much faster than I can think up what I want the code to do. Use whichever you are comfortable with but I think VHDL is much easier to learn from scratch and then once you learn that, picking up Verilog is not so difficult.

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With this and many other FPGA platforms, you'll probably end up using the vendor's toolchain.  For Papilio, that's Xilinx ISE.  It contains its own VHDL & Verilog implementations, which are capable of generating output for Xilinx FPGAs.  There would be other ones for Altera FPGAs, etc.


See also:

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I use GHDL extensively, and by that I mean quite large designs. I even simulated Linux on ZCoreV3 using GHDL (a few hours to simulate a few ms).

The only problem is you cannot simulate some of hard-ip cores, like MCB. For those you need to use FUSE (the simulator that comes with ISE), but performance will be degraded if your design is considered "too big". Which most are, by the way.


Believe it or not, I use Modelsim at work and I often export waveforms so to use GTKWave for visualization and exporing. Modelsim (and ISe waveviewer) are unfortunately a pain to work with.



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