flag26838 Posted October 7, 2015 Report Share Posted October 7, 2015 I don't understand why this register file: entity reg16_8 is Port ( I_clk : in STD_LOGIC; I_en : in STD_LOGIC; I_we : in STD_LOGIC; I_selA : in STD_LOGIC_VECTOR (2 downto 0); I_selB : in STD_LOGIC_VECTOR (2 downto 0); I_selD : in STD_LOGIC_VECTOR (2 downto 0); I_dataD : in STD_LOGIC_VECTOR (15 downto 0); O_dataA : out STD_LOGIC_VECTOR (15 downto 0); O_dataB : out STD_LOGIC_VECTOR (15 downto 0));end reg16_8;architecture Behavioral of reg16_8 is type store_t is array(0 to 7) of std_logic_vector(15 downto 0); signal regs: store_t := (others => X"0000");begin process(I_clk) begin if rising_edge(I_clk) then if I_en='1' then if I_we='1' then regs(to_integer(unsigned(I_selD))) <= I_dataD; end if; O_dataA <= regs(to_integer(unsigned(I_selA))); O_dataB <= regs(to_integer(unsigned(I_selB))); end if; end if; end process;end Behavioral; if run against this test bench: ... -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; wait for I_clk_period*10; -- insert stimulus here I_selA <= "000"; I_selB <= "001"; I_selD <= "000"; I_dataD <= X"BEEF"; I_we <= '1'; I_en <= '1'; wait for I_clk_period*10; wait; end process;... takes two clock cycles to update the O_dataA bus - IOW, after 200ns my test bench starts, all input signals are set and i expect at the first rising edge of the clock (205ns), the ouput of the register file to be update, in particular i expect O_dataA to take the value of I_dataD, but that doesn't happen until another clock cycle passes (215ns), when my process() in the register file is executed again. Aren't the staments inside a process executed sequentially? So if i set a register as the first thing in a process(), i expect later statements to pick up this change, am i right? I guess no, since that's not what is happening... Quote Link to comment Share on other sites More sharing options...
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