Kyp069 Posted September 3, 2015 Report Share Posted September 3, 2015 Hi all, Please, apologies for my bad English. I am building a clone of a ZX Spectrum computer. It was a Zilog Z80 based computer with some custom hardware for video displaying very popular here in Spain in the 80s. I already have a basic working implementation using FPGA's BRAM. Using an ArcadeMegawing it displays a VGA video signal, reads a PS/2 keyboard, plays audio and also, with a simple adapter, can load game from tapes. Since I have already used all available BRAM but I need more to implement some other things (DivMMX emulation, a way to load games from a SD card), I need to use the SDRAM chip onboard. I have read about using SDRAM like if it was SRAM in other topic in this forum. There is said it is possible but only at slow speeds. No problem then because mi clone runs at 3.5 MHz. I am figuring how to use Hamster's SDRAM controller but I am having no success on it. I have wrote this small module to test reading/writing to SDRAM. It writes an incremental value and then reads it. I use the LEDs to see if it is working. I know that the module goes through all three states (send write command, send read command, wait to data is retrieved... then repeat for every memory address) because if I tie LEDs to address signals they display appropriate data (or at least I think they lit as they should, some kind of binary count) but if I tie the LEDs to the read data signal they are always on. I don't know what is wrong with this. Any help is appreciated.library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;entity top is port ( netCLK : in std_logic; -- netLED : out std_logic_vector( 3 downto 0); -- sdramCLK : out std_logic; sdramCKE : out std_logic; sdramCS : out std_logic; sdramRAS : out std_logic; sdramCAS : out std_logic; sdramWE : out std_logic; sdramBA : out std_logic_vector( 1 downto 0); sdramADDR : out std_logic_vector(12 downto 0); sdramDQM : out std_logic_vector( 1 downto 0); sdramDATA : inout std_logic_vector(15 downto 0) );end;architecture behavioral of top is signal clock : std_logic; signal ready : std_logic; signal enable : std_logic := '0'; signal wr : std_logic; signal a : std_logic_vector(20 downto 0); signal di : std_logic_vector(31 downto 0); signal do : std_logic_vector(31 downto 0); signal dr : std_logic; signal addrwr : std_logic_vector(20 downto 0) := (others => '0'); signal addrrd : std_logic_vector(20 downto 0) := (others => '0'); signal datawr : std_logic_vector(31 downto 0) := (others => '0'); signal datard : std_logic_vector(31 downto 0); type statetype is (sendwrite, sendread, waitread); signal state : statetype := sendwrite;begin netLED <= datard(23 downto 20);-- netLED <= addrrd(20 downto 17); process(clock) begin if rising_edge(clock) then if enable = '1' then enable <= '0'; else case state is when sendwrite => if ready = '1' then enable <= '1'; wr <= '1'; a <= addrwr; di <= datawr; addrwr <= addrwr+1; datawr <= datawr+1; state <= sendread; end if; when sendread => if ready = '1' then enable <= '1'; wr <= '0'; a <= addrrd; state <= waitread; end if; when waitread => if dr = '1' then datard <= do; addrrd <= addrrd+1; state <= sendwrite; end if; end case; end if; end if; end process; Uclock : entity work.clock port map ( i => netCLK, o => clock ); Usdram : entity work.sdram_controller generic map ( sdram_address_width => 22, sdram_column_bits => 8, sdram_startup_cycles => 10100, cycles_per_refresh => (64000*100)/4196-1 ) port map ( clk => clock, reset => '0', -- interface to issue reads or write data cmd_ready => ready, cmd_enable => enable, cmd_wr => wr, cmd_address => a, cmd_byte_enable => "1111", cmd_data_in => di, data_out => do, data_out_ready => dr, -- sdram signals SDRAM_CLK => sdramCLK, SDRAM_CKE => sdramCKE, SDRAM_CS => sdramCS, SDRAM_RAS => sdramRAS, SDRAM_CAS => sdramCAS, SDRAM_WE => sdramWE, SDRAM_BA => sdramBA, SDRAM_DQM => sdramDQM, SDRAM_ADDR => sdramADDR, SDRAM_DATA => sdramDATA );end; Quote Link to comment Share on other sites More sharing options...
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