hroyster Posted August 31, 2015 Report Share Posted August 31, 2015 I am relatively new to the Design Lab use. I get the following error when I try to compile the examples in Xilinx ISE. The following error messoge comes up. "ERROR:HDLCompiler:410 - "C:\_Data\Papilio\Projects\Multiple_Serial_Ports\circuit\LX9\Papilio_Pro.vhf" Line 223: Expression has 148 elements ; expected 201" It looks as though there is a mismatch in the bus dimensions. Am I doing something wrong? I chose papilio pro from the board selector. I tried several of the examples and the bus mismatch still remains. Thanks in advance for any help. Quote Link to comment Share on other sites More sharing options...
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