Flash loading after reset


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I am happily loading .bit files into the Papilio DUO using the command-line tool "papilio-prog", like this:

$ papilio-prog -v -d 'Papilio DUO' -f xilinx/j1-papilioduo.bitUsing built-in device listJTAG chainpos: 0 Device IDCODE = 0x24001093     Desc: XC6SLX9Created from NCD file: j1-papilioduo_par.ncd;UserID=0x09470947Target device: 6slx9tqg144Created: 2015/08/13 10:43:45Bitstream length: 2724832 bitsUploading "xilinx/j1-papilioduo.bit". DNA is 0x995bf8001a2215ffDone.Programming time 503.7 msUSB transactions: Write 176 read 8 retries 7

This is working fine.


But when I power-cycle the DUO, I would expect it to load the same bitstream from flash. Instead it doesn't seem to run. Is there something I am doing wrong?



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Hello James,


That method only loads to the FPGA and bypasses the SPI flash chip. There should be a -b option where you will provide the location to the bscan_spi_lx9.bit file. That will load a bit file that provides a bridge from jtag to the SPI device and loads your user bit file to SPI Flash.



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