ZPUino 2.0 VHDL Simulation

[fun2fpga]

Hi,

 

I'm trying to run a VHDL simulation of the ZPUino v2 code I downloaded from Github.  In my simulation environment, I've included the ZPUino v2 code and a model of the SDRAM. (However, I've not yet included a model of the SPI flash as I'm not sure how to load it and am uncertain if it's actually necessary.)  

 

In my simulation, I've also loaded the SDRAM at adress 0x1000 with a .hex (converted from .bin) version of my Arduino program.  In simulation, I'm able to see the bootloader being accessed, but not long after it's completed the bootloader access, my simulation ends.  What should I expect next in my simulation?  I was expecting to see the program counter access the SDRAM at address 0x1000.  

 

Thanks for any help! 

 

 

[alvieboy]

Simulation is always tricky, because you don't want the real life behaviour - for example, before loading the sketch from flash to RAM the bootloader waits for one second. This one second, if simulated, will take *ages*.

 

So, for SDRAM/sketch, we use another approach, which is a different bootloader that jumps right to SDRAM @0, after enabling it.

 

for SDRAM, you'll need a properly generated .srec file.

 

Do you have any "trace.txt" that I can look at  so to see what is preventing your simulation from running ?