MrCrusty Posted July 1, 2015 Report Share Posted July 1, 2015 Now I am getting old, hit 70 this year, so the old grey cells aint what they were. I have followed the learning thread on this. Have been able to complete the process so that the Xilinx makes the new bit file. Process nice and simple Xilinx ISE has no errors. Problem occurs when I return to DesignLab, If I ask to view the design I get a message that the bit file is newer than the design held and DesignLab opens up the blank design. If I edit file then Xilinx ISE opens with the deign I have built. If I load the bit file I do not get the expected reaction from the Papilio from the button and led wing. Not so worried about this at the moment as getting the design to update would be a great move forward. Any advice would be good. Best Crusty Quote Link to comment Share on other sites More sharing options...
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