Another FPGA circuit design


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Now I am getting old, hit 70 this year, so the old grey cells aint what they were.


I have followed the learning thread on this.


Have been able to complete the process so that the Xilinx makes the new bit file. Process nice and simple Xilinx ISE has no errors.


Problem occurs when I return to DesignLab, If I ask to view the design I get a message that the bit file is newer than the design held and DesignLab opens up the blank design. If I edit file then Xilinx ISE opens with the deign I have built.


If I load the bit file I do not get the expected reaction from the Papilio from the button and led wing. Not so worried about this at the moment as getting the design to update would be a great move forward.


Any advice would be good.


Best Crusty


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Hello Crusty,


Unfortunately the view the design icon does not update dynamically. It is mostly meant for designs that I have already provided, when you are editing your own design then the "View Design" icon is not going to update to the design that you edited. We are working on functionality to have this update dynamically but it will take some time to complete it.


When you edit your design are you double clicking on the "Generate Programming File" in the Xilinx editor?


Here is a tutorial showing you step by step what to do:


And here is the step to Generate the Programming File:



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Thanks again for the fast response.

It's good to know that I am getting it right so far with DesignLab.


I think it must be the I/O ports I am specifying for the design, so I will have another go later on today.

The generate bit file in ISE, I am used to, as I used it on earlier Papilio one board.


I know the ports are ok as the led and switch wing works with the Papilio Duo quickstart sketch when loaded.


It took me about a month to get my head around Papilio One board when I first got it, so probably it will take about the same time for Duo.


It does not help that I am also working on PSoC 5 Creator IDE at the same time.




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