Myndale Posted June 25, 2015 Report Share Posted June 25, 2015 I'm just starting out with FPGA's so apologies if this is a bit of a noob question but I'm having trouble understanding the relationship between DCM clocks and their effect on static timing. I've designed a circuit to run at 100MHz. If I run it directly off the 32MHz Papilio Pro clock the static timing report states a minimum period of 4.992ns/200.321MHz. However, as soon as I add a DCM to bump the clock up to 100MHz the report drops to 16ns/62.5MHz, even though the circuit itself appears to operate fine at that speed. Furthermore this DCM timing result remains the same even If I strip my design down to a single flip-flop. I'm assuming that either I'm setting something wrong in the DCM core generator or I'm misunderstanding the static timing report (i.e. it applies to the incoming clock, not the DCM output). If the former, can anyone suggest what I might be doing wrong? If the latter, how do I go about testing the maximum frequency of my designs without disconnecting them from the DCM every time? Quote Link to comment Share on other sites More sharing options...
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