Question about the toolchain and open source

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I just saw this project, and it looks really cool. I especially love that it is open source and hackable. I saw an answer on stackoverflow about FPGA's that suggested that a lot of proprietary tools were needed to use any FPGA, and this had me worried. I was wondering, what proprietary software is needed (if any) to develop and create designs for the Papillio? Is it possible to do anything useful using only open source software?


Thanks for the help!

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Xilinx - WebPACK


it is free but not OSS.


you should check out the Papilio DesignLab posts (this is the current one but you want to check out the getting started parts)


jack also has some nice youtube videos.


there is a walkthrough on how to get everything running.


sorry for the short answer but busy @ work


// F

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Is there anything like the icestorm project in the works for the Xilinx fpgas?

The best work I've seen for reverse-engineering Xilinx is "From the bitstream to the netlist" by Jean-Baptiste Note and Éric Rannaud.  The paper is quite a few years old and I don't know if their software is available anywhere or how complete the implementation was.  They used Xilinx Design Language (XDL) as their Rosetta Stone.


There's also my Flavia project, but I only change look-up tables, flip-flop init bits, and I/O pin pull-up/down and keeper config bits.  Flavia is a tool for learning about programmable logic and your are limited to CPLD-level logic complexity.  I don't touch or reverse-engineer the routing.  Xilinx has provided a bitgen option for locating LUTs and FFs, so it seemed I could play with those without risking legal problems.  When you do IceStorm's level of reverse-engineering in the USA you can expect legal problems.  They should be safe in Austria.


Here are some Flavia links if you're interested:


I think IceStorm is pretty amazing and I'm going to take a close look at it.  I looked at the Lattice iCE40 a couple years ago and IIRC it's a simple, clean architecture.  Having a documented bitstream makes iCE40 very interesting indeed.

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do you think it could be easily applied to the papilio arcade stuff?   i wanted to see about a way to change the arcade dip switches before uploading to the fpga, without recompiling the whole thing but couldnt figure out a way to do it.


(sorry for the thread hijack)



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i want to change dipsw the same way we merge the roms into the bitstream without recompiling, but without using brams. :)


I'm not familiar with the Papilio Arcade, so these are general comments.


If you have a register in your design and want to change how it's initialized without resynthesizing, there's a couple ways to do it.


1.  You can open the Xilinx FPGA Editor, which lets you edit the post-place&route design graphically.  Find your register (not too hard if it has a distinctive name), open up the logic cells, and change the set/reset configuration.  Then generate a bitstream from the changed design, which I believe you can do in the FPGA Editor.


2.  You can also use Xilinx Design Language (XDL), which may or may not be in your ISE release.  Try running "xdl" from the command line.  If it's there, it will give you some help information.  Xilinx's FPGA Editor uses an NCD (Native Circuit Description) file, an undocumented binary format.  XDL translates NCD into an ASCII representation, which you can then edit using a text editor or any other text-processing program.  Then you can translate XDL back to NCD and run bitgen to get a new bitstream.


There's a small problem translating Spartan-6 XDL back to NCD, at least for ISE 12.4.  XDL -ncd2xdl inserts extraneous "PRE_EMPHASIS::#OFF" attributes.  You need to delete them before converting back to NCD or DRC fails.


3.  Once you have two bitstreams, you can compare them with a binary compare and see where the init bits actually are in the bitstream.  Then you can go in and modify them individually, and generate a new bitstream.  However, you also need to produce a new CRC for the bitstream, which is fairly easy once you know how.  My Flavia project (post #6 above) uses this technique.


Hope this helps!


Disclaimer: modifying bitstreams at this level can potentially create a bitstream that could damage your FPGA or connected circuits.  My comments are offered WITHOUT WARRANTY and if you use my suggestions you must agree that I have NO LIABILITY if something goes wrong.

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