Simple Pulse Generator outputting pulse groups instead


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I am new the FPGA and picked up a Papilio Pro. Going through a tutorial I found, I am attempting to create a pulse generator. My code is as follows:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity pulse_gen is    Port ( CLK_SYS : in  STD_LOGIC;           CLK_OUT : out  STD_LOGIC);end pulse_gen;architecture Behavioral of pulse_gen is    signal sample_counter: std_logic_vector(7 downto 0);begin    sample_process: process (CLK_SYS) is    begin        if rising_edge(CLK_SYS) then            if sample_counter = 207 then                CLK_OUT <= '1';                sample_counter <= (others => '0');            else                CLK_OUT <= '0';                sample_counter <= sample_counter + 1;            end if;        end if;    end process;end Behavioral;

Seems simple enough. This should generate a steady stream of pulses by counting up to 207 then resetting to zero and counting again. However, when logic probing to see the results after loading to the board, I am not getting a steady stream. What I get is about 80 to 81 62.5nS wide pulses (6.5uS period) followed by 656.5uS of no activity (low signal). The pattern just repeats, a stream of about 80 or so pulses then low signal.

The 6.25nS width makes sense. 35MHz = 31.25nS Period. 31.25x2 accounts for the 2 clock cycles for the signal to go high and low again, as described in the sample_process. And the period of the pulses measured at 6.5 uS, can be explained by 207 x 31.25 = 6,468.75nS. Close enough (I think). But I cannot explain the  656.5 of no output between the pulse groups.

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I have a couple things to say about this. In general I don't think it makes sense to not initialize your counter. You can either use a reset signal or when you declare the signal assign it to zeros using := (others => '0'). You should do this because it will likely fail the =207 condition and then go to the increment but from what? It is undefined. I think you would get all 'X' in simulation which you should be doing if you have behavioral questions about your design. The initialization will not likely change what you are seeing it is just a better practice. As far as your issue, what are you using for your logic analyzer? What is the sample rate? It sounds like it may be an aliasing problem, make sure you are sampling >2 times your fastest pulse. Do a sim (after initializing sample_counter) and convince yourself it works then figure out what went wrong in hardware.

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I've just now tried this out on my Papilio and it seems to work fine.  I get one cycle of "high", 207 cycles of "low", repeat.  I don't think minor the modifications I made did anything.  So I suspect your VHDL is ok and the real problem is "downstream" from there.


Things to consider:

  • treadstone's suggestion of aliasing in your logic analyzer:  See what happens if you change your sample rate.
  • Is your output signal going to the pin you think it's going to?  In your project directory, look for a file whose name ends with _pad.txt.  It was created by ISE, and it'll tell which signal goes where.  Open it in a text file viewer and search for a line with your signal name (e.g., CLK_OUT).   It'll appear on the second column of the line.  And on the first column of the line, you'll have the FPGA pin number.  I mention this because one of my early FPGA designs (perhaps my first) somehow got the wrong pin numbers for things, which meant nothing worked.  Deleting the "project" in ISE and putting my HDL code in a new project, somehow magically made it work.
  • Do the same thing with your clock signal; on the Papilio Pro it should appear on "P94".
  • Is the code you're running what you think you're running?  If you changed your design and didn't rebuild, or for some reason loaded an old bitstream instead of the new one, you could see some surprising results.

That's all I've been able to think of.  None of them seem super likely to me, I'm afraid, to match what you've been seeing.


(In case you're wondering what modifications I made:  I added a "clock enable" signal to your VHDL, and wrapped it in a little module of my own.  The end result ran your code at 75Hz instead of 32MHz, and transmitted the output to my computer at 1200 baud as '0' and '1' characters.  It would've been a lot easier if I hadn't messed up my own counter, and got 75baud and 600baud before finally getting the 1200 I was trying for.)

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Hi MamboDee,


Remote debugging is always fun ;)


Can you also post your constraints (.ucf) file? Then we can check what pins you are using.


I assume you are using the on-board oscillator, which is 32MHz not 35MHz.(just a typo because you have the right period: 31.25ns)


What are you expecting the result to look like? It should be 153.8KHz clock that is high for 31.25ns then low for 6468.75ns. Is this what you are expecting?


Could you post a screen shot or photo of what you are seeing?



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Thanks everyone for the replies. Sorry to make you wait.

It turned out to be my logic analyser was not keeping up. I went out and got a Digilent CMod S6. This board runs at 8MHz. After loading the same exact same code, the wave form came out as expected. I then did some research and loaded up the papilio pro with a DCM that cuts the speed down to 8MHz. The papilio pro works like a champ also.

After some frustrating math and and trying to figure out how the world works, it turns out the 62.5ns pulse width combined with the slight difference in speed between the oscillator of the board and the logic analyser caused a rolling variation of just enough for the samples to catch the pulses for a few ticks and then miss for a few ticks. A lesson learned indeed.

Some notes: Yes, I had a reset and the counter was initialized. All the extra trimmings were in the tutorial code. But when the results were not as expected, I wanted to remove as much as possible while trying to troubleshoot the issue. My logic analyser is the Saleae Logic (the first one). It only works reliably up to 16Msps on my pc. I thought 16Msps would be good enough, but after this adventure, I think I can talk my wife into letting me get one of the new models :D

Thanks again, and please forgive my noobness. Gotta start somewhere.

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Hello MamboDee,


Please note that you can also use the Papilio as a Logic Analyzer up to 200Mhz. The LA is built into the latest version of DesignLab, just click on the OLS icon in the toolbar. If you want to embed a Logic Analyzer into your FPGA design then there are schematic symbols to do so in the library. No need for an external logic analyzer like the Saleae you can avoid connecting any wires by just using DesignLab and connecting the probes in your FPGA design directly.


I should be making a video about this very soon.



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