MamboDee Posted June 17, 2015 Report Share Posted June 17, 2015 I am new the FPGA and picked up a Papilio Pro. Going through a tutorial I found, I am attempting to create a pulse generator. My code is as follows:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity pulse_gen is Port ( CLK_SYS : in STD_LOGIC; CLK_OUT : out STD_LOGIC);end pulse_gen;architecture Behavioral of pulse_gen is signal sample_counter: std_logic_vector(7 downto 0);begin sample_process: process (CLK_SYS) is begin if rising_edge(CLK_SYS) then if sample_counter = 207 then CLK_OUT <= '1'; sample_counter <= (others => '0'); else CLK_OUT <= '0'; sample_counter <= sample_counter + 1; end if; end if; end process;end Behavioral;Seems simple enough. This should generate a steady stream of pulses by counting up to 207 then resetting to zero and counting again. However, when logic probing to see the results after loading to the board, I am not getting a steady stream. What I get is about 80 to 81 62.5nS wide pulses (6.5uS period) followed by 656.5uS of no activity (low signal). The pattern just repeats, a stream of about 80 or so pulses then low signal.The 6.25nS width makes sense. 35MHz = 31.25nS Period. 31.25x2 accounts for the 2 clock cycles for the signal to go high and low again, as described in the sample_process. And the period of the pulses measured at 6.5 uS, can be explained by 207 x 31.25 = 6,468.75nS. Close enough (I think). But I cannot explain the 656.5 of no output between the pulse groups. Quote Link to comment Share on other sites More sharing options...
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