stm Posted March 29, 2015 Report Share Posted March 29, 2015 Hi, I'm workingt on getting started with the DesignLab and ISE workflow, and for that I'm trying to build a simple project without ZPUino. I created a new DesignLab project, edited the circuit in ISE, deleted the ZPUino and everything else from the schematic. I then built a minimal circuit with a clk_divider_30to1hz symbol from the Papilio libraries. I can create a bit file, upload it to the Papilio DUO, and after connecting two LEDs to the configured pins I have two LEDs flashing at 1 Hz and 8 Hz as expected. As a next step I'm trying to run the circuit in the ISim simulator, and I haven't been able to make that work yet. I created a new VHDL test bench, and I added a process for the CLK signal. When I'm starting the simulation, the following warnings appear when the simulation is built:WARNING:HDLCompiler:89 - "C:/Users/stm/Documents/DesignLab/divider/circuit/DUO_LX9/Papilio_DUO_LX9.vhf" Line 68: <clk_divider_30to1hz> remains a black-box since it has no binding entity.WARNING:Simulator:648 - "C:/Users/stm/Documents/DesignLab/divider/circuit/DUO_LX9/Papilio_DUO_LX9.vhf" Line 68. Instance clk_divider_30to1hz is unbound In the wave window the two outputs from the clk_divider_30to1hz symbol appear with an "U" in the "Value" column (see attached screen shot). If I understand it correctly, this means that the two outputs are uninitialzed. Is there any additional configuration necessary in order to run a ISim simulation for a DesignLab project that uses symbols from the Papilio libraries? My test project is also available via DropBox if someone is interested: https://www.dropbox.com/s/loctq3jnw0kz1av/divider.zip?dl=0 ThanksStephan Quote Link to comment Share on other sites More sharing options...
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