Editing the schematic symbol + offtopic timing question

Tony Ivanov

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Hey Guys!


I'm a bit new to this level of development but it intrigues me well into the dead of the night. 


So I've set out to design a Papilio wing of my own in-order to experience most of what this science has to offer, and so far I've managed to get everything to work as it should.


With the exception of my schematic symbol... how do i get the wishbone-connectors to be placed nicely at the top of my module just like all the other wishbone-components that are bundled with DesignLab? 

Here's wat my symbol looks like right now:


As you see the wishbone_in and wishbone_out buses get placed at the sides which I find a bit inconvenient..



Question nr 2:

I'm a bit unsure whether or not my thoughts are correct,  I'm using an external ADC ic, It's capable of producing 100k samples per second at 2MHz, where each sampling takes 20 clocks. 

As I'm using 96k samples/sec to read audio from ADC-Channel0, am I correct in assuming that it should be possible to squeeze in an additional 4k samples/sec to read the other ADC channels without affecting/interrupting the timing of the audio? 


Thanks for hearing me out.


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Hello Tony and thank you for working on making a DesignLab library. It's a bit of rough going right now since it's a pretty new concept so thank you for your patience. 


To move the wishbone connectors to the top you should be able to right click on the schematic symbol and choose "Symbol/Edit Symbol" which will let you schematically change the symbol in any way you want. The other option is that the sym file is an xml file that you can modify with a text editor.


For question 2, its sounds reasonable to expect that, but others in the forum have way more experience with that sort of thing and can maybe chime in. How are you reading the ADC? SPI?



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Thanks Jack, that helped! Now I just need to figure out how to rotate the bus-glyphs so they point upwards but that's minor. 


On a sidenote you guys have done wonders with the Designlab IDE, actually I got my papilio almost 2 years ago, but interfacing my hardware design with the zpuino-core had a too steep learning curve for me back then. ( I spent almost two weeks studying the design theories before I shelved my project ) 

So It's kindof proof that you're headed the right way since I managed to get this far in less than a week. Keep it up! :) 

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