New DesignLab Library - Quadrature Decoder


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Hi everyone,

I have a Mobile Robot and want to track wheel turns with Papilio DUO, but I have some approach questions/problems :)  .


 I need to use the 5v tolerant pins. (because of the encoder).  If I use the ZPUno the project would be like the Papilio_Duo_quick_Start, but with different code and only the 5v pins?


But if I decide to  use only VHDL:

- after I write the code and create a schematic symbol do I have to connect it to the ZPUno or I can remove the ZPUno and proceed like a traditional FPGA project and schematic ? If the answer is that I have to connect the two, what communication should I implement?




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Hello Filip,


You can completely delete the ZPUino Soft Processor and proceed like a traditional FPGA project. Please take a look at the Divider_Example project in DesignLab for an example of this. For the divider_example the AVR chip is used to generate a clock, but that is not necessary either. It's totally fine to use just the FPGA for your project without the ZPUIno or the AVR chip. 


In fact, I was just thinking about this thing last night. I need to provide examples/templates for these different use cases:

  • A ZPUino Soft Processor project
  • A straight FPGA circuit project
  • An AVR for code and FPGA for circuit project.

I intend to include templates for all these scenarios in the next release.


I'm going on a vacation next week so I might be slow to respond in the forums, but please post any questions here and I will help as much as I can.



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Hello Jack,


Thank you for your answer! Have a nice vacation  :)


I thought more about my project and I think I will use the ZPUino, cause I need to implement also P-regulators/ or just for communication with other Arduinos (have two more on the Robot) -> I will post results/question as I make progress :)


For now :

I had a look at, for example -  it is the Multiple_serial_ports example, but I can not find the HardwareSerial library to see how REGISTER(IO_SLOT(wishboneSlot),1); works ( I mean why register 1 and not 2 ).

till now I only can view this code:

 signal  wb_clk_i:    std_logic;                     -- Wishbone clock  signal  wb_rst_i:    std_logic;                     -- Wishbone reset (synchronous)  signal  wb_dat_i:    std_logic_vector(31 downto 0); -- Wishbone data input  (32 bits)  signal  wb_adr_i:    std_logic_vector(26 downto 2); -- Wishbone address input  (32 bits)  signal  wb_we_i:     std_logic;                     -- Wishbone write enable signal  signal  wb_cyc_i:    std_logic;                     -- Wishbone cycle signal  signal  wb_stb_i:    std_logic;                     -- Wishbone strobe signal    signal  wb_id_o:    std_logic_vector(15 downto 0);    signal  wb_dat_o:    std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)  signal  wb_ack_o:    std_logic;                      -- Wishbone acknowledge out signal  signal  wb_inta_o:   std_logic;	 begin-- Unpack the wishbone array into signals so the modules code is not confusing.  wb_clk_i <= wishbone_in(61);  wb_rst_i <= wishbone_in(60);  wb_dat_i <= wishbone_in(59 downto 28);  wb_adr_i <= wishbone_in(27 downto 3);  wb_we_i <= wishbone_in(2);  wb_cyc_i <= wishbone_in(1);  wb_stb_i <= wishbone_in(0);

If I understand it correctly there is the following - ZPUno - register - wishboneslot - FPGA ?

I looked also at the ZPUuno pdf manual - but is there some wiki on the wishbone slots and the registers for each slot? 




As for the templates :

  • A ZPUino Soft Processor project   - is that not the Papilio_Duo_quick_Start example ?
  • A straight FPGA circuit project 
  • An AVR for code and FPGA for circuit project.



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Take a look at:


This is the reading process. It uses the 2th bit (note that bit 1 and 0 are not used, because we have a 32-bit width bus, and unaligned accesses are not permitted).


So, for register N, the address (wb_adr_i) used is (only lower 8-bits shown, including bit 0 and bit 1) :

N=0 -> "00000000".

N=1 -> "00000100".

N=2 -> "00001000"

N=3 -> "00001100"

... so on.


So, back to reading process:


  process(wb_adr_i, received_data, uart_busy, data_ready, fifo_empty, fifo_data,uart_intx)  begin    case wb_adr_i(2) is      when '1' =>        wb_dat_o <= (others => Undefined);        wb_dat_o(0) <= not fifo_empty;        wb_dat_o(1) <= uart_busy;        wb_dat_o(2) <= uart_intx;      when '0' =>        wb_dat_o <= (others => '0');        wb_dat_o(7 downto 0) <= fifo_data;      when others =>        wb_dat_o <= (others => DontCareValue);    end case;  end process;

Depending on the 2th bit, it will return different data. 


This is the writing process:

  process(wb_clk_i)  begin    if rising_edge(wb_clk_i) then      if wb_rst_i='1' then        enabled_q<='0';      else        if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then          if wb_adr_i(2)='1' then            divider_rx_q <= wb_dat_i(15 downto 0);            enabled_q  <= wb_dat_i(16);          end if;        end if;      end if;    end if;  end process;

This time, we only act upon writes whose bit 2 is '1', so that mean register "1" (and all odd registers - they are mirrored to save implementation space).


We could compare all of "wb_adr_i", but it's expensive and does not actually have a good reason for doing it.



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Thanks for the reply Alvie :)


I made a test library -  since I won't have access to the encoders till Monday I used two buttons from the Button/Led Wing as A and B signals - which doesn't work (good) but I will debug/change code on Monday.   (+ I'm not sure which will be the best clock)


Till today I somehow missed the Wishbone_to_Registers.vhd file :( (it was there) but I guess I used it now, the way it is supposed to be used.


Things I bumped into:

- Wishbone_to_Registers.vhl and Papilio_DUO_LX9.sch were not in my work library - they were in Designlab. When I wanted to create a symbol the vhdtdtfi complained it can't find them.

- in the example .ino file I had to write #define circuit Encoder_test to be able to upload the .bit file. Maybe this can be written automatically as a comment in the auto-generated example file.


Will post updates next week.



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Hello all,


everything is ok, it works :)  . I even added 3 more encoders (packed as one vhdl module) for the other wheels.



1. is there a policy for posting libraries ? for example I would make a new topic and post the "end version" there. (can it be uploaded to "my media" on the forum or should it be external link/github  ?)


2. Jack, how do you edit the wishbone signals in the schematic symbol editor ?  when I put them on top I get an error that it is not permitted to be on top ?

(update on this question) saw this topic - will try to edit the xml file. :)

(update 2)  Successfully edited with the editor and the xml file :) - (Tip: for the editor the actual pin is a small square under the line)


3. Is there a bug tracker for designlab, where one could post/help out? (may be ? )




Edited by Filip
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Hey Filip,


This is exciting, yours will be the first contributed library for DesignLab! I've setup this showcase location where people can list the libraries they have created:


I would recommend uploading a zip of the library there, include the github link in the description. Then post about it in the forum and I'll make a blog post. If you are interested, I will also give you access to if you want to make a tutorial about using the library.


The Github Issues is the place we have standardized on tracking bugs.


Thank you for your library!



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Hi Jack,


I will try to wrap things tomorrow and post it on Friday :) .  A tutorial would be great, cause I could also show how I use it with a PID regulator (using the PID arduino library on ZPUno) for controlling the wheels. This weekend I will be away, but I hope I could write it + make videos next week.  I'm not a native English speaker, so maybe I should send you the text/videos first for review ?


Jack, Alvie and the others who I don't know - I should thank you, not you me :) cause without your work there would be no possibility for the library :) .. so thanks




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I just took a look at the quadrature decoder library you made. It looks good, there are just a couple minor issues that I fixed up and submitted a pull request to you on Github. 


I was able to test your quad decoder "chip" with a project of my own and the Encoder Wing and it worked perfectly! Great job. :)



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