About FPGAs and how to choice

[Yaro]

Hi all,

 

I know this topic is not related to any forum, but I'm new at FPGAs and want to learn more about them.

 

First of all, all FPGA are same? I mean, if I buy an FPGA from one producer or another, I can always use same HDL programming languages?

 

Since I've alweys used MCUs, how I can understand FPGA calculation power and clock?I know that I programm logic gates, but I've seen someone have emulated MCUs on an FPGA. What I ask is, can I emulate an Atmel chip(8MHz-8bit) on a 10k logic gates FPGA or I need 100k? can I use any clock on an FPGA? What are parameters that I can use to understand FPGA logic power?

[Jaxartes]

Re FPGA capability, short answer: It's complicated.  And I'm almost a newbie, but here are some thoughts and pointers.

 

For figuring out what a given FPGA can do, the best way is to look at what results people have gotten from trying similar designs on similar FPGAs.  Somewhere on the forum there're discussions about resource usage and clock rate with AVR8 (an Atmel-compatible core) running on a Papilio board; the results may extend to other boards using the same FPGA chips.

 

You can download vendor tools, and run them on an actual design (for whatever chips you have in mind) and see what results they give you.

 

The general story is more complicated than number of gates or any straightforward set of numbers.  It's going to depend on the particular FPGA architecture and the particular design and how the features of one make the other work.  For instance, logic on the Xilinx Spartan3 (used in Papilio One) consists primarily of 4-input lookup tables (LUTs), while that on the Xilinx Spartan6 (used in Papilio Pro and Duo) is in 6-input LUTs.  A 6-input LUT is "more logic" than a 4-input LUT, but it'd be hard to quantify how much more.  Either one is more than a 2-input "gate" but again, by how much?

 

And FPGAs have other, more specialized logic in addition to the LUTs: Block RAM, carry chains, multipliers.  It can make a big difference, how well your design takes advantage of those.

 

10k gates sounds really small.  Even 100k gates sounds small; the smallest that the Papilio series uses is 250k gates.

 

Clock rate also can vary a lot, depending again on the particular logic design and how it fits into the FPGA's particular resources.  It can vary pretty widely.  8MHz doesn't seem like a problem, though, for recent chips.

 

Choosing an FPGA board often comes down to other things, for me it was what I/O devices are attached to it, and how it connects to a host computer.

 

I found "100 Power Tips for FPGA Designers", by Evgeni Stavinov, very helpful.  The e-book edition is much cheaper than the print one, by the way.  (Code examples are in Verilog, but code examples aren't IMO the most important part.)

[james1095]

To expand on that, HDL is generally portable between different FPGA vendors BUT many times code will take advantage of vendor-specific features like block RAM, clock generators, multipliers and such and that ends up being non-portable. Also there can be timing differences and other variations so complex designs often need some work to port from one platform to another.

 

The two big players are Xilinx and Altera. Lattice also makes FPGAs and CPLDs but they don't seem to have much hobbyist support. You might start by trying out the tools, Xilinx ISE and Altera Quartus II and see which one you prefer. The hardware of a given generation has similar capabilities but the software is what you spend your time interacting with.

[Yaro]

But how are related logic gates to logic implementation. For example, with 100k gate I can emulate an MCU? or I can just create some logic connections? Or, how much logic gates I need to create a NAND or a PLL or another logic device? and this number of logic gates I use is known and always same?

[james1095]

It varies. FPGAs are made of logic blocks, if you look at the datasheet it will show you what these blocks consist of. The number of blocks used by a particular component depend on a lot of factors. For reference, a 6502 CPU fills about 10% of a 500K gate Spartan3. Xilinx calls their PLLs DCMs and they are blocks of dedicated hardware within the FPGA. The 500k Spartan3 has four of them. You can fit an entire 8 bit computer in one of these parts with room to spare.