Dokur23 Posted March 11, 2015 Report Share Posted March 11, 2015 PapilioOne.ucf# Constraints for the Papilio OneNET CLK32M LOC="P89" | IOSTANDARD=LVTTL | PERIOD=31.25ns; # CLKNET phase_a LOC="P91" | IOSTANDARD=LVTTL; # C0NET phase_b LOC="P92" | IOSTANDARD=LVTTL; # C1NET phase_c LOC="P94" | IOSTANDARD=LVTTL; # C2NET phase_d LOC="P95" | IOSTANDARD=LVTTL; # C3NET sw_dir LOC="P11" | IOSTANDARD=LVTTL; # C15NET sw_enable LOC="P15" | IOSTANDARD=LVTTL; # C13NET sw_speed LOC="P17" | IOSTANDARD=LVTTL; # C11Hello everyone,Can anyone help me what these pins are on Papilio One. I am using Xilinx Spartan 6 FPGA board. Can anyone suggest me what pins on Spartan 6 match with the above UCF file of Spartan 3e. Source: http://hamsterworks.co.nz/mediawiki/index.php/Stepper Quote Link to comment Share on other sites More sharing options...
Jack Gassett Posted March 12, 2015 Report Share Posted March 12, 2015 Hello, you need to find the documentation for whatever board you are using and figure out what pins connect to what. We cannot help you much without knowing what the board is or what the schematic for the board is. You should be able to look at the schematic, or a ucf file for the board, and see that FPGA pin P1 connects to a certain pin on a header on the board. Then you will modify your ucf file accordingly. Jack. Quote Link to comment Share on other sites More sharing options...
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