Aha!

[james1095]

I'd seen work.xxxx entities in a number of projects but I haven't found a good explanation in any of the tutorials I've encountered. After chatting with someone who does FPGA development for a living I finally understand it. Turns out Component declarations aren't generally used unless you are attaching a Verilog component to a VHDL file. Instead, each source file you add to a project is automatically added to the default working library. That means that you can skip the component declaration and just instantiate the component as my_entity_name: entity work.component_name where my_entity_name is a unique name you choose for that specific entity, for example "CPU" or "Audio_DAC" and component_name is the name of the component that you're attaching to the top level. You can create your own custom libraries as well but the default working library is automatically created. Once you get the hang of this it's simple, and it really cleans up the code vs having a bunch of redundant Component declarations. I don't know why it isn't more widely documented.

[alvieboy]

It has advantages, and disadvantages.

 

The disadvantage is that, if you design an entity that uses another entity, and you want to depict exactly what that other entity is, you should declare your component, to to avoid misunderstandings on the interface. (but this may fail too)

 

The advantage is obvious - less clutter, easier to maintain.  I am using that approach in my new designs, despite not using mixed-language.

 

Alvie