vhdl/xilinx ise questions: reusing chip code, automatic log() of generics and a PULLUP warning

[flag26838]

Hi forum,

 

still on my quest to learn VHDL and FPGA, i finally manged to build my own rs232 controller, but now

i've some miscellaneous questions about VHDL and the Xilinx ISE:

 

1) isn't there a way to reuse a previously built chip wihout phisically copying the src code? (e.g. Project -> Add copy of source)

In software development you can link your objects against the objs in another directory, fundamentally reusing previously written code, what's the equivalent with the xilinx ise? is that possible at all?

I really want to avoid fragmentation.

 

2) generics are really useful, but i really hate the idea that i need to specify, for example, an interger value and the number of bits necessary to represent it:

 

entiry mod_m_counter is

generic(

    M: integer := 10; -- mod-M

    N: integer := 4 -- # bits to represent M

);

 

and in the upper level chip using this:

 

generic (

    DVSR: integer := 104;

    DVSR_BIT: integer := 7

);

...

baud_generator: mod_m_counter

GENERIC MAP(

    M => DVSR,

    N => DVSR_BIT

)

 

isn't there a way to automatically calculate N in the mod_m_counter?

 

3) while building the tx part of an rs232 controller, i got this warning:

 

WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp tx_PULLUP

   is set but the tri state is not configured. 

 

what does that mean?

 

...

NET TX             LOC="P105" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # TX

...

 

on a papilio pro + logicstart megawing - besides, the tx part works.

[alvieboy]

 

entiry mod_m_counter is

generic(

    M: integer := 10; -- mod-M

    N: integer := 4 -- # bits to represent M

);

 

 

You can use this (or a similar approach):

library ieee;use ieee.math_real.all;entity mod_m_counter is generic(    M: natural := 10; ) --- bla bla end entity;architecture (...) of mod_m_counter is  function numbits(width: in natural) return integer is    variable r: integer;  begin    r := integer(ceil(log2(real(width))));    return r;  end function;  constant N: integer := numbits(M);end (...)

[Tb_]

 

3) while building the tx part of an rs232 controller, i got this warning:

 

WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp tx_PULLUP

   is set but the tri state is not configured. 

 

what does that mean?

 

...

NET TX             LOC="P105" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # TX

...

 

on a papilio pro + logicstart megawing - besides, the tx part works.

 

 

You probably configure the pin "tx" as an output and PULLUP option doesn't have sense in this context.

By googleing :

http://forums.xilinx.com/t5/Spartan-Family-FPGAs/PULLUP-on-an-active-net/td-p/143378

 

Thomas

[alvieboy]

Simple:

 

you have a PULLUP on an output-only pin, which does not make sense, since it cannot ever go tristate. So just remove pullup from the constraint.

 

Anyway, you can safely ignore the warning.