Gadgetoid Posted February 11, 2015 Report Share Posted February 11, 2015 I've been quite successfully working through the Intro to Spartan FPGA book on the Duo. It's a damned good book that still holds up after being around for a number of years- although you have to approach it with patience, and be well armed with Google and these forums. Due to a total lack of time, I've only made it as far as adding two 4-bit numbers - input via the switches - and displaying the result on the LEDs. It works, but a little note in the book suggests that IEEE.NUMERIC_STD.ALL is now the defacto way to add numbers. I think this is the solution, it's pieced together from what I could turn up on Google:result <= std_logic_vector(resize(unsigned(x),5) + resize(unsigned(y),5));I suspect it's not as succinct or "correct" as it could be though! Clocks I distinctly remember there being a guide somewhere for using the FPGAs clock generators, but I ignored it and implemented a 32bit clock divider with a user-configurable tap... VHDL strong typing is painful!library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL;entity Switches_LEDs is Port ( SW : in STD_LOGIC_VECTOR(4 downto 0); LED : out STD_LOGIC_VECTOR(7 downto 0); CLK : in STD_LOGIC );end Switches_LEDsarchitecture Behavioral of Switches_LEDs is signal pll: STD_LOGIC_VECTOR(31 downto 0); signal tap: STD_LOGIC; signal counter: STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); signal speed: STD_LOGIC_VECTOR(4 downto 0);begin speed <= SW; tap <= std_logic(pll(to_integer(unsigned(speed)))); LED <= std_logic_vector(resize(unsigned(counter),8)); pll_proc: process(CLK) begin if rising_edge(CLK) then pll <= std_logic_vector(unsigned(pll) + 1); end if; end process; clk_proc: process(tap) begin if rising_edge(tap) then counter <= std_logic_vector(unsigned(counter) + 1); end if; end process;end Behavioral; Quote Link to comment Share on other sites More sharing options...
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