Working through Intro to Spartan FPGA on the DUO + LogicStart Shield


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I've been quite successfully working through the Intro to Spartan FPGA book on the Duo. It's a damned good book that still holds up after being around for a number of years- although you have to approach it with patience, and be well armed with Google and these forums.


Due to a total lack of time, I've only made it as far as adding two 4-bit numbers - input via the switches - and displaying the result on the LEDs. It works, but a little note in the book suggests that IEEE.NUMERIC_STD.ALL is now the defacto way to add numbers.


I think this is the solution, it's pieced together from what I could turn up on Google:

result <= std_logic_vector(resize(unsigned(x),5) + resize(unsigned(y),5));

I suspect it's not as succinct or "correct" as it could be though!





I distinctly remember there being a guide somewhere for using the FPGAs clock generators, but I ignored it and implemented a 32bit clock divider with a user-configurable tap... VHDL strong typing is painful!

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL;entity Switches_LEDs is    Port (        SW : in STD_LOGIC_VECTOR(4 downto 0);        LED : out STD_LOGIC_VECTOR(7 downto 0);        CLK : in STD_LOGIC    );end Switches_LEDsarchitecture Behavioral of Switches_LEDs is    signal pll: STD_LOGIC_VECTOR(31 downto 0);    signal tap: STD_LOGIC;    signal counter: STD_LOGIC_VECTOR(7 downto 0) := (others => '0');    signal speed: STD_LOGIC_VECTOR(4 downto 0);begin    speed <= SW;    tap <= std_logic(pll(to_integer(unsigned(speed))));    LED <= std_logic_vector(resize(unsigned(counter),8));    pll_proc: process(CLK)        begin            if rising_edge(CLK) then                pll <= std_logic_vector(unsigned(pll) + 1);            end if;        end process;    clk_proc: process(tap)        begin            if rising_edge(tap) then                counter <= std_logic_vector(unsigned(counter) + 1);            end if;        end process;end Behavioral;
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One thing about clock generation is that using a logic signal as a clock (as in 'rising_edge(tap)' above) is discouraged in FPGAs.  As I understand it (which is limited, I'm still sort of a newbie) one of the problems is:  Logic is sometimes "glitchy" (temporary bogus output values that last less than a clock cycle, and thus wouldn't matter, unless you use them as a clock).  Another has something to do with routing and timing analysis.


One alternative, if you want to run part of your circuit slower than your clock, is to use a clock enable.  Suppose, for example, "CLK" is your clock and "en" is a signal that's HIGH for one out of every five clock cycles.  Then you'd do the following:


if rising_edge(CLK) and en = '1' then

    do <= stuff;

end if;


(Please pardon any syntax mistakes, I mostly use Verilog and am unfamiliar with VHDL.)

The FPGA hardware has special support for handling this sort of thing.

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This makes sense! Thank you, I'll have to give it a go. I can see the logic behind it, and I think I can implement it in VHDL pretty easily.


I also need to look up the guide for using the proper clock generator too, it's a much saner way of generating a usable clock.


Aha, found the tutorial I followed once-upon-a-time here:

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Thank you! I'm not ready to do any serious VHDL just yet, but I'm eager to learn the "right way" of doing things if at all possible.


Right now I'm just throwing stuff at the wall and seeing what sticks, probably picking up some bad habits, and generally trying to wrap my head around the whole concept of hardware design.


I'm eager to see an updated book, but certainly not in a hurry. Ignoring all the other stuff I've got to do, the Papilio Duo is a damned good device even if you never touch a line of HDL!


I've managed to adapt the example in the link I posted to the LX9 and have a working clock divider down to 1mhz, which is a little more manageable for tinkering.

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