Corey Kosak Posted February 11, 2015 Report Share Posted February 11, 2015 I came across this project today and thought you folks on the forum might find it entertaining. Amazing what you can do with an FPGA http://www.chrisfenton.com/homebrew-cray-1a/ Link to comment Share on other sites More sharing options...
Jack Gassett Posted February 11, 2015 Report Share Posted February 11, 2015 This would be a good project for the Papilio DUO and the computing shield. Jack. Link to comment Share on other sites More sharing options...
Corey Kosak Posted February 11, 2015 Author Report Share Posted February 11, 2015 Hm, really? I think the author is using a much larger FPGA. Link to comment Share on other sites More sharing options...
Jack Gassett Posted February 11, 2015 Report Share Posted February 11, 2015 Ah! I didn't see that he is using the 1600 Spartan 3E Starter kit board... I'm very surprised it would take that large of a chip though. I wonder if he is using distributed RAM or something and that is what is needing so much FPGA fabric. It would be worth taking a look at the code to see if we could fit it in the spartan 6. Jack. Link to comment Share on other sites More sharing options...
Jack Gassett Posted February 12, 2015 Report Share Posted February 12, 2015 I'm pretty rusty with Verilog but it looks like the project is implementing 32KB worth of memory as FPGA registers!https://code.google.com/p/cray-1x/source/browse/trunk/Verilog/cray1/cray_sys_top.v That would explain why it takes so much space, if we used SRAM instead it should fit in the DUO. Jack. Link to comment Share on other sites More sharing options...
Corey Kosak Posted February 12, 2015 Author Report Share Posted February 12, 2015 We live in exciting times! One issue might be that his project is using a 64-bit-wide data bus. The DUO's SRAM data bus is 8 bits right? Adapting to this cause this DUO-based Cray to run a tad slower. Link to comment Share on other sites More sharing options...
james1095 Posted February 12, 2015 Report Share Posted February 12, 2015 You could try wiring up an external SRAM chip to any of the Papilio FPGA boards. Another possibility is grafting on the SDRAM controller to make use of the RAM chip on the Papilio Pro. Link to comment Share on other sites More sharing options...
mkarlsson Posted February 12, 2015 Report Share Posted February 12, 2015 No need for SDRAM or any other kind of external RAM, it only uses 32 kB of RAM. But you need a big FPGA...I did a port of this way back in 2013 and it used up 71% of the slices in the LX45 on Pipistrello. Magnus Edit: see attached Xilinx summary filecray_sys_top_summary.html Link to comment Share on other sites More sharing options...
james1095 Posted February 12, 2015 Report Share Posted February 12, 2015 We're talking in context of the Papilio though, the Pro has a Spartan6 LX9. I just looked up the specs and it seems it has more BRAM than I had remembered, 32 blocks of 18Kb which works out to 72kB so that should be enough depending on whether it uses any other RAM or ROM. If it uses that many slices of the LX45 then there's no way it's gonna fit though, unless the high usage is due to using slices instead of BRAM for RAM. Link to comment Share on other sites More sharing options...
mkarlsson Posted February 13, 2015 Report Share Posted February 13, 2015 I looked at the report again and it looks like it only used two of the 2KB rams and 18 of the 1KB rams so I think you are right.Maybe he is using non-registered RAMs? If you want to play with it, here is a link to a zip file with the Pipistrello version (I cleaned it up):http://www.saanlima.com/download/pipistrello-v2.0/cray-1.zip Link to comment Share on other sites More sharing options...
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