monsonite Posted February 8, 2015 Report Share Posted February 8, 2015 This is a popular course in computer design, devised by Noam Nisan and Shimon Schoken, where starting with the simple NAND gate, a whole modern 16 bit cpu can be designed from first principles. http://www.nand2tetris.org/ I ploughed my way through the first 5 chapters of the book in a week, but have to admit that my software skills were not up to scratch for progressing the projects in the 2nd half of the book. I did however learn a lot on the journey and actually learned how processors work. I think that access to modern FPGA hardware, DesignLab and Papilio would be a great way of teaching this essential skill to a whole new generation of potential Digital Designers. So Jack, what do you think? Could we see Papilio hardware used in this most worthy educational programme? Ken Link to comment Share on other sites More sharing options...
Jack Gassett Posted February 10, 2015 Report Share Posted February 10, 2015 Hey Ken, This looks totally awesome! I looked over the first couple of chapters and the website in order to better understand how the Papilio could contribute. This is a great course for people who want to learn about FPGA's. The first couple of chapter's covered stuff that I wish I would have known when I first started learning FPGA's. So what are your thoughts on how the Papilio could fit in here? It looks like the course is taught with a hardware emulator, so making it all work on real hardware might be more rewarding... I also wonder if there is a desire to turn the components into schematic symbols in DesignLab so people could work through the examples schematically.. Of course, any project that has something called, "Jack OS" is going to get my interest! Jack. Link to comment Share on other sites More sharing options...
monsonite Posted February 10, 2015 Author Report Share Posted February 10, 2015 Jack The hardware simulator was a neat way of making all the tools "self contained" - and free to use for students. I think that there would be tremendous merit to implementing this as an exercise in CPU design - but on a modern and low cost FPGA. Having done the various exercises, I re-worked out the whole design in the form of a bit slice, which contained the program counter, the ALU and the various memory buses. I got as far as an eagleCAD schematic, that given sufficient pcbs and TTL chips, the design could be realised in real hardware. At about that point, your Papilio Duo Kickstarter went live - and I put the project on the back shelf, and decided to wait for the Duo, so that the multiple bit-slice design could be implemented sensibly and cheaply on an FPGA. Now that the Duo is available, and has the added benefit of the various shields (LogicStart, retro-computing etc) plus the ZPUino, the SRAM and the 32U4 all on board as support hardware, it now makes the whole project look a lot more practical - allowing the ZPUino to act initially as a supporting processor with audio and VGA to make the business of getting a CPU running from scratch a whole lot easier. It would be a great tutorial exercise in DesignLab to allow students to work through the various components, offering preworked solutions, to which they can compare their trial designs. Perhaps if we also put together the bit-slice as a schematic element in DesignLab, then the whole CPU could be designed either using individual components blocks - or as a step and repeat bit-slice. I've attached the bit slice .sch and brd files - so you can see how straightforwards it mightbitslice_2.zip be to implement form basic gates and D-types let me know your thinking. Ken London Link to comment Share on other sites More sharing options...
Jack Gassett Posted February 10, 2015 Report Share Posted February 10, 2015 Ah, ok, so after looking at the EAGLE project I see what you are thinking. One of the things that I read was that the author's asked that people don't publish finished solutions. But I think if we provided schematic based symbols for each of the building blocks and then make the building blocks with VHDL then it would allow people to go through the coursework using a schematic approach. Since each successive block will be built with VHDL and they will be using the schematic then it won't provide an easy to copy example... I think paired with the LogicStart it would be a tremendous way to get people started with FPGA technology. We should check in with the author's first and make sure it would fit in with what they envisioned. Jack. Link to comment Share on other sites More sharing options...
monsonite Posted February 10, 2015 Author Report Share Posted February 10, 2015 Jack & Forum I just found the various VHDL designs for the NAND2Tetris project on GitHub https://github.com/kzzch/nand2tetris-vhdl Perhaps someone with a bit more free time, and VHDL experience than I have - could evaluate these. Thanks in advance Ken London Link to comment Share on other sites More sharing options...
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