Seba Posted January 7, 2015 Report Share Posted January 7, 2015 Hi, I am new to the FPGA and thinking about ordering Papilio One 500K.I am wondering weather is it possible to connect soft processor (ZPUino) to external ram through papilio I/O pins like for instance DDR memory?Well I know that papilio doesn't have near enough I/O ports but with shift registers it could be done? Is this in theory possible, even with longer wait time for memory response?It would be quite fun project Quote Link to comment Share on other sites More sharing options...
hamster Posted January 7, 2015 Report Share Posted January 7, 2015 Possibly? Yes. Practical? No.The speed of signals needed to operate a SDRAM chip property make this impractical. If you were to run you serial interface at 100MHz, and used ram with a 16 bit data bus the SDRAM chip would be clocked at about 6MHz. There are however static RAM chips with a serial interface that could be used, that require only three or four wires. Quote Link to comment Share on other sites More sharing options...
Seba Posted January 7, 2015 Author Report Share Posted January 7, 2015 Cool, i know there would be quite alot of perfomance dropdown on the processor but I don't quite care that much about that.It would be cool to have arduino-like platform with GBs of RAM maybe to slowly run emulators Anyway, thank you for your quick response! Quote Link to comment Share on other sites More sharing options...
hamster Posted January 8, 2015 Report Share Posted January 8, 2015 GBs might be expecting a bit much. Here's an example part for you http://www.microchip.com/mymicrochip/filehandler.aspx?ddocname=en559112 It has some funny 2-data-pin DDR mode, where you can get 10MB/s out of it. Not too shabby. Quote Link to comment Share on other sites More sharing options...
Seba Posted January 8, 2015 Author Report Share Posted January 8, 2015 Yes, I am familiar with those SRAM chips, infact I already used them on arduino few years ago (but 32KB ones) but here I'm just wondering what would it take to actually get DDR/2 socket module, some bunch of shift registers and plugging actual ram for desktop which contains storage in GBs. I know it would be pretty difficult since those ram modules have their minimum speed limit but maybe by having a seperate core in FPGA that takes care of RAM calls it might reach those limits? I know that what I'm asking would be very impractical and who knows weather I'll actually make it work but I like doing that kind of projects that seem very pointless Quote Link to comment Share on other sites More sharing options...
Jack Gassett Posted January 9, 2015 Report Share Posted January 9, 2015 I actually did something along these lines once using a CPLD. http://papilio.cc/index.php?n=Papilio.CRAMWing In the case of the CRAM Wing I wanted to use it to add more memory to the Logic Sniffer. Since the Logic Sniffer always just counted the memory address up or down it was possible to eliminate all of the address lines and just have data that was incremented or decremented. It worked perfectly but I never actually released it as a product. I had also thought about schemes where you send the address you want in one cycle and then read back or write the data in the next cycle. Jack. Quote Link to comment Share on other sites More sharing options...
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