Papilio DUO/Pro/One possible application

[vacaloca]

I'm a bit of a beginner in the FPGA world and wanted to ask a few questions in regards to the Papilio DUO and how it compares to the One/Pro models. I'm fairly confident it will work for our design and the price point is right, but wanted to ask a few questions before purchase.

 

First a bit of background. We currently have an Arduino Mega 2560 R3 taking a clock signal as an input (164 microsecs/pulse) and we drive an electrical switch with five TTL outputs from the Arduino depending on which port we want to sample from. Important point - data only is contained on the rising edge of the clock signal, and this is what we acquire with our digitizer board... more on that below.

 

Currently we interface with the Arduino via its native serial port -- we store some settings in it's EEPROM according to a configurable LabView VI. Next, a second program is loaded that reads those stored EEPROM values and outputs the logic signals that drive the switch and outputs a 'state line' which indicates which port we are sampling from. This 'state line' and switch output are jointly digitized with a PC board at 5MHz.

 

An important point is that our input/output clock signals are TTL logic (0 V = LOW, 5 V = high) compatible. From what I can tell, FPGA pins are meant to take in at most by default, which could be solved by a voltage divider, just at first thought, but my understanding is that converting 3.3V -> 5V will need external circuitry if the switch needs close to 5V instead of 3.3V to trigger a 'high' signal.

 

Because the Arduino method is only so flexible, we want to move to an FPGA to be able to expand our design to additional switch modules which require additional outputs to drive them. Another perk of the FPGA is that (I assume) we should be able to send a serial command to start executing the code, and reset it after either some time or clock pulses has elapsed (more likely easier) or reset it via another serial command sent to it.

 

Or for that matter, we'd like to use another TTL encoder signal to start/stop executing the code -- i.e. when the FPGA sees the first pulse of that signal, it starts cycling through the switch output states, and when the pulse train ends, it stops cycling, resets to the initial state and waits until the next pulse is seen to start over again. This approach would eliminate the need to sample the 'state line' mentioned previously. The encoder signal can be a higher frequency than the clock signal, but not even close to our digitizer's sampling rate. Estimating, for every clock rising edge, the encoder signal has at most 4 pulses in our application.

 

Now that the background is out of the way, here are the questions:

 

1) Do I have an advantage/reason to use a particular Papilio board for the above implementation?

1a) One possible advantage for the DUO -- we are currently using a screw shield for easily connecting wires to the Arduino 2560 Mega R3, so I assume this would be compatible with the DUO

1b) From what I understand the DUO has the additional software to (more) easily prototype circuit design called DesignLab. However, when I look at the promo video, that functionality seems to exist in the Xilinx ISE with the Papilio libraries, even with older boards. Is DesignLab a separate software? Is it only compatible with the DUO or will it work with Pro/One boards, and if it is separate, how does it differ from using the Papilio libraries in Xilinx ISE?

1c) Do I benefit from additional SRAM? What is SRAM used for specifically in the FPGA? Is that related to the number of logic devices/gates that can be programmed at the same time, or... ? (sorry. noob question and I can't seem to find an answer online)

1d) If I pre-order a Papilio DUO board now, when should I expect to receive it?

 

2) What sort of circuitry could we use to achieve TTL 0-5V output capability on the output pins driven by the FPGA design done by ISE/DesignLab, if needed? (each clock signal pulse lasts 164 microsecs)

 

3) Before I stumbled upon your design, I found the Mojo dev-board, which seems very similar to the Papilio line of boards. What advantage(s) do the Papilio boards have over that other alternative? (I don't necessarily expect an answer to this in the forum, you can PM one if you'd like or edit my post to remove this question altogether if you feel like it, haha)

 

4) Not related to the Papilio itself, but... in the future we might want to time multiplex an analog LF (up to 5MHz) signal before it gets sent to the digitizer. (i.e. the output a signal not connected to a switch, sampled every 0.2 microseconds) Would a mux like this work? https://www.sparkfun.com/datasheets/IC/CD74HC4067.pdf

 

I think that about covers everything.

[johnbeetem]

I'll try to address the 3.3V question.  While TTL is a 5V family, the actual signal voltages are lower than that.  Specifically, If something is truly "TTL compatible", it means that 0.8V or less is Logic 0 and 2.0V or more is Logic 1.  TTL outputs are 0.4V or less for Logic 0 and 2.4V or more for Logic 1, which gives you 0.4V noise margin.  So the TTL logic levels are compatible with 3.3V CMOS, provided that you protect 3.3V inputs from 5V unless they're "5V tolerant".  (Spartan-6 inputs aren't.)

 

Very few designs use actual TTL any more -- they some form of CMOS.  5V CMOS typically swings from near 0V to near 5V, but that's compatible with a TTL input.  3.3V CMOS swings from near 0V to near 3.3V, so that's also compatible with a TTL input.  5V CMOS inputs come in a "pure CMOS" version (e.g., 74HC04) that considers anything below 30% of VDD to be Logic 0 and anything about 70% of VDD to be Logic 1.  They do not detect a 3.3V CMOS output reliably.  There are also 5V CMOS "TTL compatible" families (e.g., 74HCT04) which have the same Logic 0 and Logic 1 input levels as TTL, i.e., 0.4V and 2.0V.  These do detect 3.3V CMOS outputs reliably.

 

So you need to look at the data sheets of the 5V devices your FPGA would be driving and see if they're "pure CMOS" or "TTL compatible".  In the latter case, you won't have to do anything for FPGA outputs, and voltage dividers work fine for FPGA inputs.

 

Wikipedia has a bit about this at Logic Family

 

Hope this helps!

[johnbeetem]

3) Before I stumbled upon your design, I found the Mojo dev-board, which seems very similar to the Papillion line of boards. What advantage(s) do the Papilio boards have over that other alternative? (I don't necessarily expect an answer to this in the forum, you can PM one if you'd like or edit my post to remove this question altogether if you feel like it, haha)

 

The Mojo are Papilio Pro are very close: they use the same Spartan-6 LX9, and both provide a lot of user I/O.  Mojo provides more user I/O, but Papilio Pro gives you SDRAM, so which is better depends on your project.  Papilio has a nice set of Wings with various interfaces.  I don't know if Mojo has anything equivalent.  Mojo uses an ATmega32U4 for programming, so I guess you need to run a special PC program to download the FPGA.  Papilio uses an FTDI FT2232 which is a standard part with device drivers already loaded in newer Windows and GNU/Linux systems.

[vacaloca]

Thanks for those responses. I figured as much in re: the 3.3V, The only documentation I have available mentions: "L/H = "logic 0"/"logic 1" for +5V TTL/CMOS". I'll double check with the maker of the switches to make sure.

 

The wings offered don't seem to make a difference for what we need to use it for, although like I mentioned earlier reusing the screw terminal is nice, since we already have it, so that puts the DUO in favor at least. Good to know in re: interfaces, in this case it doesn't matter as much because I'm running Windows 7 because of the LabView interface, but if this becomes a part of a final design, the FTDI FT2232 would be a better match if some flavor of Linux is chosen as the O/S... but that's quite a while away now, haha.

[vacaloca]

Okay, so after looking at the GIT website here: https://github.com/GadgetFactory/

I think I have answered (most) of my questions...

 

1) Do I have an advantage/reason to use a particular Papilio board for the above implementation?

Yes, SRAM vs SDRAM -- SRAM is lower latency, although it might not matter for the particular application. Apparently, the biggest plus for the Duo for my application is the fact that there are shared pins that are 5V tolerant for I/O. This also answers question 2.

 

1a) Pin schematic here shows a compatible Arduino Mega 2560 R3 layout as far as I can tell, so our existing screw shield should work just fine.

1b) DesignLab seems to be the usual Arduino IDE with the extensions needed for the Papilio board and corresponding pin mappings which interfaces with Xilinx ISE and Papilio circuit libraries to enable circuit prototyping on the soft processor (ZPUino) driven by the FPGA.

1c) Some info here: http://www.fpga4fun.com/FPGAinfo3.html

Also, nice PPT here that explains memory in FPGAs. From what I understand, the 512K board would provide more than enough memory for my application.

 

2) Apparently shared 5V tolerant pins are available. After looking at the brd file with Eagle, I see at least 1 resistor on top of each of those pins, but after looking at a few techniques for level transitioning between 5V->3.3V I can't tell how it's being done.

 

3) From what I can tell, the benefit is DesignLab and perhaps easier mapping of pins if working under that paradigm. I had previously been using DigitalWriteFast when using the Arduino before, but looking at the source code of the latest DesignLab 0.20 beta under hardware\papilio\zpu\cores\zpuino there are 2 files that mention DigitalWrite: zpuino.h and zpuino-accel.S. Apparently, if the C pre-processor flag ZPUINO_ACCEL is set, the IDE uses the ZPUINO "assembly implementations for speed" for the functions that have it.

 

4) I'll probably test this on my own soon as I have one of these mux's and the output signal available, and see if it works out.

[alvieboy]

Regarding point 3, yes, most implementations use "fast" assembly code for some operations such as pin writes.

 

Anyway, if you need more speed (like ultra-fast toggling or similar) it can be achieved with a dedicated hardware (wishbone) controller.

[Jack Gassett]

Okay, so after looking at the GIT website here: https://github.com/GadgetFactory/

I think I have answered (most) of my questions...

 

1) Do I have an advantage/reason to use a particular Papilio board for the above implementation?

Yes, SRAM vs SDRAM -- SRAM is lower latency, although it might not matter for the particular application. Apparently, the biggest plus for the Duo for my application is the fact that there are shared pins that are 5V tolerant for I/O. This also answers question 2.

 

1a) Pin schematic here shows a compatible Arduino Mega 2560 R3 layout as far as I can tell, so our existing screw shield should work just fine.

1b) DesignLab seems to be the usual Arduino IDE with the extensions needed for the Papilio board and corresponding pin mappings which interfaces with Xilinx ISE and Papilio circuit libraries to enable circuit prototyping on the soft processor (ZPUino) driven by the FPGA.

1c) Some info here: http://www.fpga4fun.com/FPGAinfo3.html

Also, nice PPT here that explains memory in FPGAs. From what I understand, the 512K board would provide more than enough memory for my application.

 

2) Apparently shared 5V tolerant pins are available. After looking at the brd file with Eagle, I see at least 1 resistor on top of each of those pins, but after looking at a few techniques for level transitioning between 5V->3.3V I can't tell how it's being done.

 

3) From what I can tell, the benefit is DesignLab and perhaps easier mapping of pins if working under that paradigm. I had previously been using DigitalWriteFast when using the Arduino before, but looking at the source code of the latest DesignLab 0.20 beta under hardware\papilio\zpu\cores\zpuino there are 2 files that mention DigitalWrite: zpuino.h and zpuino-accel.S. Apparently, if the C pre-processor flag ZPUINO_ACCEL is set, the IDE uses the ZPUINO "assembly implementations for speed" for the functions that have it.

 

4) I'll probably test this on my own soon as I have one of these mux's and the output signal available, and see if it works out.

 

Regarding 2 - Series limiting resistors are used to provide the 5V tolerance which is a common technique with Xilinx FPGAs. They use it in all of their reference designs so it is well proven. 

 

Jack.