Wishbone unexpected behaviour


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Im having a problem with the wishbone interface on the ZPUino soft processor. 

I am trying to output a signal to a design I have made, in this instance its outputting a reset signal but the same problem occurs on all the other outputs too.

The signal and corresponding pin I have the oscilloscope connected to is highlighted in red in fig 1.  This goes to a custom block that builds individual signals into a bus that is outputted using the Papilio block set provided, this can be seen in fig 2.

Im using the standard ZPUino programing IDE, when I program it to output 0xff to wishbone Register 2 the output pin on the FPGA becomes high, this is shown in figure 3.  This is exactly what you would expect to happen.  


Again in fig 4 the when Register 2 is set to be 0x00 then the output on the pin connected to the oscilloscope is set to logic 0, as expected.

However in figure 5 Wishbone register 2 is set to be 0x00 for 100ms then set to 0xff for 200ms, this should produce a waveform that shows a signal that is high twice as long as low.  Though this is the comes out as the opposite, it seems that the signal is being inverted.  I can’t for the life of me work out why this is.  Similarly in fig 6 I set it to be the opposite 0xff for 200ms and 0x00 for 100ms and it does the same, inverting the signals again.


I have checked for sources of error in other places, the oscilloscope is working fine Ive tried connecting the Wishbone output directly to a pin to see if the Papilio output block was the cause this had no effect, I’ve double checked my Wishbone interface code its fine no reason to invert the output.  This also happens when the delay is increased to 20secconds and 10secconds to see if it was a timing issue and needed a steeling time, keeps inverting the signals still. 

The weird thing is that it works fine when the is no periodic signal applied and its just a DC output, if it was an inverter causing the problem that’s fine all I need to do is change my code around a bit but this is not that simple and I couldn’t work with an unpredictable output. 

Does anyone have any suggestion as to what the problem is?

Many thanks Joe








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I'm sorry for the slow response here, my wife had a baby on November 5th and I've been playing catchup ever since. 


I think maybe the best thing to do here is to simulate your wishbone code and see if that shakes anything loose. 


If you download the DesignLab Beta there should be a working wishbone simulator.



There is not much for documentation yet, but you can see it in action here:




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Hi Jack,


Congratulations on becoming a dad and thanks for the reply,  I'll investigate the cause further with the wishbone simulator.

I did find out how to solve it temporarily though, it is a latching problem. 


After some experimentation it was found that when writing to the Wishbone block it was necessary to write the data from the Zpunio twice, this made the output latch correctly. 


I used your wishbone example to create the block to control the CCD reader block, most of the code is the same with three registers 0-2 I was using 2 not that it makes any difference then that signal output was connected to the respective outputs on the block.  Somewhere between writing to the register and outputting that register value to the block output there is a problem.


Thanks Joe

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