Question about creating ucf constraints

[hib1]

I am following the intro to spartan  fpga book “first project” involving papilio one and a logicstar megawing with switches and leds.  The constraints file is:

 

# Constraints for Papilio One

NET switch_1 LOC = "P3" | IOSTANDARD=LVTTL;

NET switch_0 LOC = "P4" | IOSTANDARD=LVTTL;

NET LED_1 LOC = "P16" | IOSTANDARD=LVTTL;

NET LED_0 LOC = "P17" | IOSTANDARD=LVTTL;

 

This is mapping each led or switch on the logic start board to a pin on the papilio board.  The pin numbers on the papilio are defined, but the pins on the logic start board are not.  How can this work?

[offroad]

Hi,

 

the "LOC" field refers to FPGA pins. To find the correct value, you'd first take the logic wing schematic, and trace back the wire to the board connector. Then, take the Papilio one schematic, and continue tracing from the connector to the FPGA. There it shows a pin (ball) identifier, and that goes into the LOC constraint.

[Jack Gassett]

The LogicStart Hardware page also has a table with the pin connections.

 

Jack

[hib1]

I am asking about a specific piece of code that is already written and is in a VHDL book.  In the ucf  file I do not see how the pin numbers are defined for the logic start board.  They are only termed NET switch_1, etc. How does this allow me to generate a bit file without additonal information about the logicstart board pins?

 

 

The entire ucf file is this. how are the logicstart board pins identifed in these 4 lines of code?

NET switch_1 LOC = "P3" | IOSTANDARD=LVTTL;

NET switch_0 LOC = "P4" | IOSTANDARD=LVTTL;

NET LED_1 LOC = "P16" | IOSTANDARD=LVTTL;

NET LED_0 LOC = "P17" | IOSTANDARD=LVTTL;

[Jaxartes]

The UCF file, and the bit file generated by the ISE tools, don't need to contain the layout of the boards.  The UCF just identifies what pin on the FPGA corresponds to each of several signals in your design; and any special electrical signalling they need.

 

For instance, in 'NET switch_1 LOC = "P3" | IOSTANDARD=LVTTL;':

'NET switch_1' -- indicates that the signal is referred to in the VHDL code as "switch_1"

'LOC="P3"' -- attaches it to pin 3 on the FPGA chip

'IOSTANDARD=LVTTL' -- identifies the electrical signals used.

 

Pin 3 on the FPGA chip is connected to a particular trace on the Papilio board, and through it to a particular pin on the Papilio's expansion header.  The LogicStart MegaWing, in turn, connects that particular pin to one of the switches.  A different wing might connect it to a different device.

 

This page describes what pin is connected to what on the LogicStart: http://papilio.cc/index.php?n=Papilio.LogicStartMegaWing

 

As far as the FPGA software is concerned, it doesn't much matter what physical device it's connected to.  It just needs to know which signal in your VHDL code goes to which pin, and what kind of electrical behavior and timing it needs.

 

The downloads section of this forum has UCF files for the various combinations of Papilio and MegaWing boards.  All I did was download the one for mine, then trim off the lines for signals I'm not using in my current project.

 

(The constraints file can do a lot more than this, but I haven't tried that stuff yet and it's not really related to the question.)

[hib1]

Thanks to all for the detailed explanations.