Chris_C Posted October 23, 2014 Report Share Posted October 23, 2014 Allthough finding ISE an uphill struggle! (but I am getting there) a long term goal is to design and implement my own CPU design. I'm looking to make something small and simple yet also powerful I'd really value peoples thoughts if only just to help get another perspective here's my rough design so far...1 16bit PC4 8bit registers R0 to R3No condition codes1-3 byte instruction codes IIII RaRb NNNN NNNNCCAAAA AAAA AAAA AAAAinstruction bits (IIII)Value (NNNN NNNN)Address (AAA...) where CC is present AAA... is a signed 14bit offset (should address the bus only be 14bit 16kb probably enough?)Ra Register R0 to R3Rb Register R0 to R3Rb16 value 0 or 2 representing 16bit register (0 = R0,R1) (2 = R2,R3)if an invalid Rb16 value of 1 or 3 is used then no 16 bit value is added tothe address (code 3 possible expansion ?)IIII Size Mnemonic Description0000 1 NOP spare ?0001 1 NAND Ra,Rb Ra=Ra NAND Rb0010 1 XOR Ra,Rb Ra=Ra XOR Rb0011 1 AND Ra,Rb Ra=Ra AND Rb0100 1 OR Ra,Rb Ra=Ra OR Rb0101 1 NOT Ra,Rb Ra=Ra NOT Rb0110 1 ADD Ra,Rb Ra=Ra AND Rb0111 1 SUB Ra,Rb Ra=Ra SUB Rb1000 1 SR Ra,Rb Ra shifted right Rb bits (only bottom 3 bits of Rb used)1001 1 SL Ra,Rb Ra shifted left Rb bits (only bottom 3 bits of Rb used)1010 1 HALT1011 2 SET Ra,NNNN Ra = immidiate 8bit value1100 3 PUT ( Rb16 + ADDRESS ) = Ra Ra is stored in address + Rb161101 3 GET Ra = ( Rb16 + ADDRESS ) Ra = contents of (address + Rb16)1110 3 JMPcc Ra,Rb, PC+(A14-A0 signed) where cc (top 2 bit of address) = eq ne gt lt1111 3 JMP Rb16 + ADDRESS PC = address + Rb16Virtual instructionsJMP ADDRESS is actually JMPeq R0,R0, ADDRESS Quote Link to comment Share on other sites More sharing options...
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